Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

Abstract: The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.

Abstract: Provided is a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. The semiconductor device is provided with a test element group (TEG) that includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.

Abstract: The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.

Abstract: The present disclosure relates to a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes: an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process; and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. For example, the present disclosure can be applied to a semiconductor device or the like provided with a test element group (TEG) including: an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process; and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.

Abstract: According to the present invention, a gate electrode having a polymetal structure, that is, a lamination structure of a polysilicon film formed via a gate insulating film on a semiconductor substrate, and a refractory metal film. An electroconductive side wall made of tungsten silicide or the like is formed on a side surface of the refractory metal film which constitutes the gate electrode. The side wall serves to prevent the evaporation of the refractory metal film.

Abstract: A gate electrode having a polymetal structure which is composed of polysilicon, tungsten nitride and tungsten is formed on a silicon substrate by RIE where a silicon nitride film is used as a mask. Thereafter, a silicon oxide film of about 3 nm is formed by selective oxidation, and a silicon nitride film of about 10 nm is formed by CVD. Moreover, the silicon nitride film is etched by using the silicon substrate as an etching stopper. Thereafter, a silicon oxide film of about 6 nm is formed again by thermal oxidation, and a silicon nitride film of about 20 nm is formed by CVD. Then, the silicon nitride film is etched by using the silicon oxide film as an etching stopper.

Abstract: A semiconductor circuit device wiring is provided in which the wiring connected to a semiconductor element is composed of a crystalline material. The crystal axis direction along which nearest neighboring atoms in a single crystal constituting the crystalline material are arranged and the electric current direction through the wiring are crossed with each other at an angle of 22.5.degree. or less.

Abstract: A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out "1" level data or "0" level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing "0" level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.