Patents by Inventor Yohei Igarashi
Yohei Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817422Abstract: A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.Type: GrantFiled: November 9, 2019Date of Patent: November 14, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Yohei Igarashi
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Publication number: 20200152601Abstract: A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.Type: ApplicationFiled: November 9, 2019Publication date: May 14, 2020Inventor: Yohei Igarashi
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Patent number: 9048331Abstract: A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film.Type: GrantFiled: December 16, 2013Date of Patent: June 2, 2015Assignee: Shinko Electric Industries Co., LTD.Inventors: Kiyoshi Oi, Yoshihiro Machida, Hiroyuki Saito, Yohei Igarashi
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Patent number: 8803304Abstract: There is provided a semiconductor package that includes: a wiring board; a first semiconductor chip mounted on the wiring board; a second semiconductor chip mounted on the first semiconductor chip, wherein a size of second semiconductor chip is larger than that of the first semiconductor chip when viewed from a thickness direction of the semiconductor package; an insulating resin provided between the wiring board and the second semiconductor chip and between the wiring board and the first semiconductor chip so as to cover the first semiconductor chip; a base disposed on the wiring board to face a surface of the second semiconductor chip, wherein the insulating resin is provided between the base and the second semiconductor chip so as to cover the base.Type: GrantFiled: June 27, 2011Date of Patent: August 12, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yohei Igarashi, Yasushi Araki
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Publication number: 20140170810Abstract: A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film.Type: ApplicationFiled: December 16, 2013Publication date: June 19, 2014Applicant: Shinko Electric Industries Co., LTD.Inventors: Kiyoshi Oi, Yoshihiro Machida, Hiroyuki Saito, Yohei Igarashi
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Patent number: 8169083Abstract: A semiconductor device includes a wiring substrate having a mounting surface on which a semiconductor element is mounted. A portion of the mounting surface exposed from the semiconductor element is covered by a solder-resist layer, and an extension portion of the solder-resist layer extends from a dropping-commencing point of a liquid-state under-filling agent on the portion of the mounting surface exposed from the semiconductor element and into an area of the wiring substrate covered by the semiconductor element. A gap between the semiconductor element and the extension portion of the solder-resist layer is formed to be narrower than the gap between the semiconductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon.Type: GrantFiled: December 22, 2009Date of Patent: May 1, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yohei Igarashi
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Publication number: 20110316172Abstract: There is provided a semiconductor package that includes: a wiring board; a first semiconductor chip mounted on the wiring board; a second semiconductor chip mounted on the first semiconductor chip, wherein a size of second semiconductor chip is larger than that of the first semiconductor chip when viewed from a thickness direction of the semiconductor package; an insulating resin provided between the wiring board and the second semiconductor chip and between the wiring board and the first semiconductor chip so as to cover the first semiconductor chip; a base disposed on the wiring board to face a surface of the second semiconductor chip, wherein the insulating resin is provided between the base and the second semiconductor chip so as to cover the base.Type: ApplicationFiled: June 27, 2011Publication date: December 29, 2011Applicant: Shinko Electric Industries Co., Ltd.Inventors: Yohei Igarashi, Yasushi Araki
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Publication number: 20100155965Abstract: A semiconductor device includes: the mounting surface of the wiring substrate exposed from the semiconductor element is covered by a solder-resist layer, a part of the solder-resist layer covering the mounting surface of the wiring substrate at a dropping-commencing point at which dropping of a liquid-state under-filling agent filled in a gap between the semiconductor element and the mounting surface of the wiring substrate is commenced is extended in an area of the wiring substrate covered by the semiconductor element, and a gap between the semi conductor element at the dropping-commencing point and the vicinity thereof and an extension portion of the solder-resist layer is formed to be narrower than the gap between the semi conductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon.Type: ApplicationFiled: December 22, 2009Publication date: June 24, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Yohei Igarashi