Patents by Inventor Yohei Ishii

Yohei Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210089948
    Abstract: In a data processing method executed by a computer: inputting, in a third trained model, first output data corresponding to first input data for a first trained model to obtain second output data, the third trained model being acquired through training in which (i) output data of the first trained model is used as training data, and (ii) output data of a second trained model acquired by converting the first trained model is used as label data; obtaining first label data of the first input data; and retraining the first trained model using first differential data corresponding to differences between the second output data and the first label data.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Inventors: Yohei NAKATA, Sotaro TSUKIZAWA, Yasunori ISHII
  • Publication number: 20210031523
    Abstract: Provided is a method for manufacturing a liquid ejection head including an ejection orifice for ejecting a liquid, a substrate and a flow path forming member that is joined to the substrate to form a liquid flow path communicating with the ejection orifice, the method including: (1) forming a resin layer having a flow path mold pattern, on the substrate; (2) adding a hydrophilizing material represented by Chemical Formula 1 to an entire surface layer of the resin layer; (3) forming a covering resin layer serving as the flow path forming member, on the resin layer and forming a compatible layer containing the resin layer, the covering resin layer and the hydrophilizing material, at an interface between the resin layer and the covering resin layer; (4) forming the ejection orifice by exposing the covering resin layer; and (5) forming a flow path by removing the resin layer.
    Type: Application
    Filed: July 22, 2020
    Publication date: February 4, 2021
    Inventors: Kazunari Ishizuka, Isamu Horiuchi, Satoshi Tsutsui, Yohei Hamade, Miho Ishii
  • Patent number: 10892158
    Abstract: A manufacturing process of a semiconductor device including a SiGe channel can form a Si segregation layer for protecting the SiGe channel without damaging the SiGe channel. A manufacturing method of a semiconductor device includes: a first step for performing plasma processing on a semiconductor substrate having a silicon layer and a silicon germanium layer formed on the silicon layer under a first condition to expose the silicon germanium layer; and a second step for performing plasma processing on the semiconductor substrate under a second condition to segregate silicon on the surface of the exposed silicon germanium layer. The silicon germanium layer or layers lying adjacent to the silicon germanium layer can be etched under the first condition, hydrogen plasma processing is performed under the second condition, and the first step and the second step are executed in series in the same processing chamber of a plasma processing apparatus.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: January 12, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Makoto Miura, Yohei Ishii, Satoshi Sakai, Kenji Maeda
  • Patent number: 10885447
    Abstract: In a data processing method executed by a computer: inputting, in a third trained model, first output data corresponding to first input data for a first trained model to obtain second output data, the third trained model being acquired through training in which (i) output data of the first trained model is used as training data, and (ii) output data of a second trained model acquired by converting the first trained model is used as label data; obtaining first label data of the first input data; and retraining the first trained model using first differential data corresponding to differences between the second output data and the first label data.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 5, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yohei Nakata, Sotaro Tsukizawa, Yasunori Ishii
  • Publication number: 20200407583
    Abstract: A hydrophilic coating material including an alginic acid compound and a resin, in which the alginic acid compound is granulated and dispersed in the resin. In a coating film using the material, it is preferred that the granulated alginic acid compound is exposed on the surface. Such a hydrophilic coating film is suitable as a hydrophilization treatment film of a nozzle face surface of an inkjet recording head.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 31, 2020
    Inventors: Yohei Hamade, Satoshi Tsutsui, Isamu Horiuchi, Kazunari Ishizuka, Miho Ishii
  • Publication number: 20200407589
    Abstract: A hydrophilic coating material including an alginate compound having a bond with a silane compound is used. The material is produced by reacting a water-soluble alginate compound and a silane compound and then by adding a divalent metal ion to an alginic acid-derived carboxyl group in the reaction product.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Inventors: Yohei Hamade, Satoshi Tsutsui, Isamu Horiuchi, Kazunari Ishizuka, Miho Ishii
  • Publication number: 20200311966
    Abstract: An information processing device includes a processor. This processor: obtains at least one of first sensor data output from a first sensor and used to determine an ambient environment of a device in which a third sensor is placed, and second sensor data used to determine an orientation of this device; determines a tilt of a plane in a sensing direction of the third sensor with respect to the orientation of the device based on the at least one of the first sensor data and the second sensor data; determines, in accordance with the tilt determined, a processing target area of third sensor data output from the third sensor and used for object detection processing in the sensing direction of the third sensor; and executes the object detection processing using the processing target area determined, of the third sensor data.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Inventors: Yohei NAKATA, Ryota FUJIMURA, Takuya YAMAGUCHI, Yasunori ISHII
  • Publication number: 20200312658
    Abstract: A manufacturing process of a semiconductor device including a SiGe channel can form a Si segregation layer for protecting the SiGe channel without damaging the SiGe channel. A manufacturing method of a semiconductor device includes: a first step for performing plasma processing on a semiconductor substrate having a silicon layer and a silicon germanium layer formed on the silicon layer under a first condition to expose the silicon germanium layer; and a second step for performing plasma processing on the semiconductor substrate under a second condition to segregate silicon on the surface of the exposed silicon germanium layer. The silicon germanium layer or layers lying adjacent to the silicon germanium layer can be etched under the first condition, hydrogen plasma processing is performed under the second condition, and the first step and the second step are executed in series in the same processing chamber of a plasma processing apparatus.
    Type: Application
    Filed: April 1, 2019
    Publication date: October 1, 2020
    Inventors: Makoto MIURA, Yohei ISHII, Satoshi SAKAI, Kenji MAEDA
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Publication number: 20200209742
    Abstract: Provided is a method of producing a microstructure including: forming a resin layer from a photosensitive resin composition on a substrate; exposing the resin layer to a microstructure pattern to form a cured portion as a result of the exposure and an uncured portion as a result of non-exposure; and removing the uncured portion from the substrate through development to provide a microstructure pattern having the cured portion, wherein the photosensitive resin composition to be used contains an epoxy resin, a crosslinking agent containing a polyhydric alcohol that is bifunctional or trifunctional with respect to a terminal hydroxy group, and that is free of a perfluoroalkyl group and a perfluoroalkylene group, a photoacid generator, and a solvent.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Satoshi Tsutsui, Kazunari Ishizuka, Isamu Horiuchi, Yohei Hamade, Miho Ishii
  • Publication number: 20200152668
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Isao SUZUMURA, Kazufumi WATABE, Yoshinori ISHII, Hidekazu MIYAKE, Yohei YAMAGUCHI
  • Publication number: 20200127458
    Abstract: In a power storage system, a three-phase AC wire is connected to a three-phase AC power system. Power storage blocks, each of which includes a power storage module and a power conditioner, are connected in parallel to the three-phase AC wire. A system controller individually controls power storage blocks. The power storage modules each includes: a power storage unit; and a management unit that manages the power storage unit. The power conditioner includes a power converter and a controller. The power converter converts DC power discharged into single-phase AC power and outputs the converted AC power to two lines of the three-phase AC wire, or converts single-phase AC power received from the two lines of the three-phase AC wire into DC power and charges the power storage unit. The controller is connected to the system controller via a communication line and the management unit via a communication line.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 23, 2020
    Inventors: MASAKI KATO, NAOHISA MORIMOTO, MASAAKI KURANUKI, JUN YAMASAKI, YOHEI ISHII, KOICHI SAWADA
  • Patent number: 10601277
    Abstract: An insulated wire in which at least one layer of an insulating material is coated around a conductor, wherein the insulated wire has a part in which relative permittivity is different in a length direction or a circumferential direction in an identical coating layer and a method of producing the same, and a rotating electrical machine and a method of producing the same.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: March 24, 2020
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA MAGNET WIRE CO., LTD.
    Inventors: Yohei Ishii, Tsuneo Aoi
  • Patent number: 10573666
    Abstract: The object of the present invention is to make it possible to form an LIPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 25, 2020
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Publication number: 20200050943
    Abstract: An information processing method includes acquiring first output data for input data of first learning model, reference data for the input data, and second output data for the input data of second learning model obtained by converting first learning model; calculating first difference data corresponding to a difference between the first difference data and the reference data and second difference data corresponding to a difference between the second output data and the reference data; and training first learning model with use of the first difference data and the second difference data.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 13, 2020
    Inventors: Yasunori ISHII, Yohei NAKATA, Hiroaki URABE
  • Patent number: 10453519
    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Yuichiro Ishii
  • Publication number: 20190270765
    Abstract: Provided a polymerizable compound represented by the following Formula A-1 or Formula A-2: In Formula A-1 or Formula A-2, R1 represents an electron-donating group; n represents an integer from 1 to 5; R2 represents a hydrogen atom, a halogen atom, or —ORO, wherein RO represents a hydrogen atom, an alkyl group, or a protecting group of a hydroxy group; R3 represents a hydrogen atom or a protecting group of a hydroxy group; and X represents a structure represented by any one of Formula B-1 to Formula B-5.
    Type: Application
    Filed: November 9, 2017
    Publication date: September 5, 2019
    Inventors: Takeshi Wada, Tatsuya Saito, Yuka Ishii, Yohei Nukaga
  • Publication number: 20190236353
    Abstract: An information processing method including the following executed using a computer: obtaining a neural network model that solves a regression problem; obtaining input data and label data corresponding to the input data; compressing a network of the neural network model to obtain a compressed model; transforming the regression problem to be solved by the neural network model into a classification problem, based on information indicating performance of the compressed model, the information being calculated using the label data and output data which is obtained by inputting the input data to the compressed model; and changing a network configuration of the neural network model and transforming the label data, in accordance with the transformation from the regression problem to the classification problem.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 1, 2019
    Inventors: Yohei NAKATA, Yasunori ISHII
  • Publication number: 20190236354
    Abstract: An information processing method including the following executed using a computer: obtaining a neural network model that solves a regression problem; obtaining input data and label data corresponding to the input data; compressing a network of the neural network model to obtain a compressed model; and changing the label data and the number of nodes in the neural network model, based on information indicating performance of the compressed model, the number of nodes being assigned to the regression problem, the information being calculated using the label data and output data which is obtained by inputting the input data to the compressed model.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 1, 2019
    Inventors: Yohei NAKATA, Yasunori ISHII
  • Publication number: 20190236463
    Abstract: In a data processing method executed by a computer: inputting, in a third trained model, first output data corresponding to first input data for a first trained model to obtain second output data, the third trained model being acquired through training in which (i) output data of the first trained model is used as training data, and (ii) output data of a second trained model acquired by converting the first trained model is used as label data; obtaining first label data of the first input data; and retraining the first trained model using first differential data corresponding to differences between the second output data and the first label data.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Inventors: Yohei NAKATA, Sotaro TSUKIZAWA, Yasunori ISHII