Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract: [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Abstract: [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.