Patents by Inventor Yohei Koganei

Yohei Koganei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11283542
    Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yohei Koganei, Kiichi Sugitani
  • Publication number: 20220077937
    Abstract: An encoding device includes a processor. The processor configured to determine, based on an integer value that corresponds to a bit string of a predetermined amount, quantities for a predetermined number of individual symbol values included in a symbol sting encoded from the bit string of the predetermined amount. The processor configured to specify positions of symbols in the symbol string for the individual symbol values from the quantities for the individual symbol values and a first parameter related to a number of arrangement patterns of the symbols that corresponds to the quantities for the individual symbol values. The processor configured to generate the symbol string by assigning to the specified positions the corresponding symbol values.
    Type: Application
    Filed: July 8, 2021
    Publication date: March 10, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Yohei Koganei
  • Publication number: 20220038327
    Abstract: A communication device that generates a modulated signal with 32 QAM includes a modulator, a first encoder and a second encoder. The modulator generates a modulated signal by mapping each symbol in a data frame that includes transmission data, a first code, and a second code to a signal point among 32 QAM signal points. The first encoder encodes the data by using a first coding scheme to generate the first code. The second encoder encodes, by using a second coding scheme, a bit string formed from one specified bit in five bits allocated to each symbol in the data frame to generate the second code. The modulator performs mapping such that each pair of signal points adjacent to each other are arranged are different from each other in terms of a value of the one specified bit among the five bits.
    Type: Application
    Filed: April 28, 2021
    Publication date: February 3, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Konno, Junichi Sugiyama, Yohei Koganei
  • Publication number: 20210218496
    Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 15, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Yohei Koganei, Kiichi Sugitani
  • Patent number: 10884706
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa, Yohei Koganei, Yuji Nagai
  • Publication number: 20200366408
    Abstract: A method includes assigning a symbol corresponding to a value of each of bit strings in a frame among the symbols in a constellation of a multi-level modulation scheme, to bit strings, converting a value of each of the bit strings other than a first bit string such that a symbol closer to a center of the constellation is assigned more among symbols, generating a error correction code for correcting an error of bit strings to insert the error correction code into the first bit string, generating the first error correction code from the bit strings other than the first bit string among bit strings, in a first period in which the error correction code is inserted into the first bit string in a period of the frame, and generating the error correction code from a second bit string in another second period in the period of the frame.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yohei Koganei, KIICHI SUGITANI
  • Publication number: 20200266888
    Abstract: An optical communication apparatus includes a first monitor that monitors a first signal carried on a first polarization and outputs a first monitor value representing a transmission characteristic of the first signal, a second monitor that monitors a second signal carried on a second polarization orthogonal to the first polarization and outputs a second monitor value representing a transmission characteristic of the second signal, and a transmitting circuit that notifies a transmitting source of the first signal and the second signal of the first monitor value and the second monitor value.
    Type: Application
    Filed: January 23, 2020
    Publication date: August 20, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yohei Koganei, KAZUMASA MIKAMI, Shigeyuki KOBAYASHI, Mitsuru SUTOU, Yuji OBANA
  • Patent number: 10623137
    Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yohei Koganei
  • Publication number: 20200004505
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA, Yohei KOGANEI, Yuji NAGAI
  • Patent number: 10459691
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa, Yohei Koganei, Yuji Nagai
  • Publication number: 20190052401
    Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Yohei Koganei
  • Publication number: 20180074791
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA, Yohei KOGANEI, Yuji NAGAI
  • Patent number: 9825731
    Abstract: An optical transmission system includes a first optical transmission apparatus that adds a plurality of error correction codes to a main signal, retrieves, from a first error correction code that is added to the main signal and that corresponds to a first sub-carrier among the plurality of sub-carriers, a first code portion in excess of a predetermined redundancy level, distributes the first code portion to a second sub-carrier among the plurality of sub-carriers, concatenates a second code portion into the first error correction code, and transmits an optical signal including the main signal multiplexed with the first error correction code that has been concatenated with the second code portion.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: November 21, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Taizo Maeda, Yohei Koganei, Ichiro Nakajima
  • Publication number: 20160336965
    Abstract: An error correction method of executing error correction for a coded signal using a space coupling LDPC, includes setting a column weight in a column direction of an element matrix that among element matrices of the space coupling LDPC, corresponds to one end side of a bit string of the signal, to be large as a parity check matrix for detecting errors in multiplying the signal.
    Type: Application
    Filed: April 6, 2016
    Publication date: November 17, 2016
    Applicants: FUJITSU LIMITED, Mobile Techno Corp.
    Inventors: Yohei KOGANEI, Chikara Kojima, Cong Li
  • Patent number: 9467318
    Abstract: A communication system includes a transmitting device that transmits a signal based on pluralities of symbol coordinates on a constellation and pluralities of trajectory coordinates between respective ones of the pluralities of symbol coordinates, average coordinates of the pluralities of trajectory coordinates being different coordinates from coordinates of origin, and a receiving device that accumulates pluralities of trajectory coordinates between respective ones of the pluralities of symbol coordinates on the constellation in the signal received from the transmitting device, and estimates a phase of the signal received from the transmitting device based on a value representing a difference between average coordinates of the pluralities of trajectory coordinates accumulated and the different coordinates.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 11, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Daijiro Tanaka, Yohei Koganei
  • Publication number: 20160261368
    Abstract: An optical transmission system includes: a first optical transmission apparatus configured to add an error correction code (ECC) having a code length in accordance with transmission quality of each of sub-carriers forming a super channel to a main signal, retrieve, from the ECC added to the main signal on a sub-carrier to be processed, a code portion in excess of a predetermined redundancy level, distribute the code portion to another sub-carrier, and concatenate the code portion of the ECC to be added to a main signal on the another sub-carrier into the ECC added to a main signal on the sub-carrier to be processed; and a second optical transmission apparatus configured to concatenate the cord portion of the ECC distributed from another sub-carrier into the ECC included in the optical signal, and decode a main signal in the optical signal on a corresponding sub-carrier by using the concatenated ECC.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 8, 2016
    Inventors: Taizo MAEDA, Yohei Koganei, ICHIRO NAKAJIMA
  • Patent number: 9438461
    Abstract: A communication system includes a transmission device that transmits a signal, based on a plurality of symbol coordinates on a constellation, which characterize a shape having a predetermined rotational asymmetrical shape, and a receiving device that accumulates symbol coordinates on the constellation in the signal received from the transmission device and estimates the phase of the signal received from the transmission device, based on a difference between the direction of a shape characterized by the accumulated symbol coordinates and the direction of the predetermined shape.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Daijiro Tanaka, Yohei Koganei
  • Publication number: 20150295747
    Abstract: A communication system includes a transmission device that transmits a signal, based on a plurality of symbol coordinates on a constellation, which characterize a shape having a predetermined rotational asymmetrical shape, and a receiving device that accumulates symbol coordinates on the constellation in the signal received from the transmission device and estimates the phase of the signal received from the transmission device, based on a difference between the direction of a shape characterized by the accumulated symbol coordinates and the direction of the predetermined shape.
    Type: Application
    Filed: March 11, 2015
    Publication date: October 15, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Daijiro TANAKA, Yohei Koganei
  • Publication number: 20150295740
    Abstract: A communication system includes a transmitting device that transmits a signal based on pluralities of symbol coordinates on a constellation and pluralities of trajectory coordinates between respective ones of the pluralities of symbol coordinates, average coordinates of the pluralities of trajectory coordinates being different coordinates from coordinates of origin, and a receiving device that accumulates pluralities of trajectory coordinates between respective ones of the pluralities of symbol coordinates on the constellation in the signal received from the transmitting device, and estimates a phase of the signal received from the transmitting device based on a value representing a difference between average coordinates of the pluralities of trajectory coordinates accumulated and the different coordinates.
    Type: Application
    Filed: March 27, 2015
    Publication date: October 15, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Daijiro Tanaka, Yohei Koganei
  • Patent number: 8839070
    Abstract: A plurality of error correction circuits connected in series include a calculator circuit that corrects the codeword when the determination results of a determination circuit indicate that the error correction circuit at the present stage is to correct the codeword, and a determination circuit at a subsequent error correction apparatus determines whether the error correction circuit at the subsequent stage is to correct the codeword when the determination results of the determination circuit indicate that the error correction circuit at the present stage is not to correct the codeword.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Yohei Koganei