Abstract: A communication device that generates a modulated signal with 32 QAM includes a modulator, a first encoder and a second encoder. The modulator generates a modulated signal by mapping each symbol in a data frame that includes transmission data, a first code, and a second code to a signal point among 32 QAM signal points. The first encoder encodes the data by using a first coding scheme to generate the first code. The second encoder encodes, by using a second coding scheme, a bit string formed from one specified bit in five bits allocated to each symbol in the data frame to generate the second code. The modulator performs mapping such that each pair of signal points adjacent to each other are arranged are different from each other in terms of a value of the one specified bit among the five bits.

Abstract: A signal processing device includes: a memory; and a processor coupled to the memory and configured to: perform soft decision of a value of, among bit strings, a predetermined bit string encoded with a soft decision code from a symbol assigned to, according to each value of the bit strings, the bit strings having been subject to encoding of an outer code with a turbo product code and encoding of an inner code with the soft decision code; decode the predetermined bit string with the soft decision code on a basis of a result of the soft decision; individually perform, from the symbol, the soft decision of a value of each bit string other than the predetermined bit string among the bit strings; and decode the bit strings with the turbo product code on a basis of a result of the decoding and a result of the soft decision.

Abstract: Encoder circuit encodes information bits using 22N signal points. The encoder circuit includes: symbol mapper that allocates each symbol of frame including information bits, first code and second code to a corresponding signal point among 22N signal points according to mapping pattern; converter that converts information bits in other bit strings among N bit strings forming the frame excluding MSB string by using probabilistic shaping; first encoder that generates the first code from information bits in MSB string and the information bits converted by the converter; and second encoder that generates the second code from the information bits in MSB string and the first code. In the mapping pattern, values of bits corresponding to the other bit strings are arranged symmetrically in the constellation, and each pair of adjacent signal points on the constellation are different from each other in terms of value of bit corresponding to MSB string.

Abstract: A signal processing device includes: a memory; and a processor coupled to the memory and configured to: perform soft decision of a value of, among bit strings, a predetermined bit string encoded with a soft decision code from a symbol assigned to, according to each value of the bit strings, the bit strings having been subject to encoding of an outer code with a turbo product code and encoding of an inner code with the soft decision code; decode the predetermined bit string with the soft decision code on a basis of a result of the soft decision; individually perform, from the symbol, the soft decision of a value of each bit string other than the predetermined bit string among the bit strings; and decode the bit strings with the turbo product code on a basis of a result of the decoding and a result of the soft decision.

Abstract: An encoding device includes a processor. The processor configured to determine, based on an integer value that corresponds to a bit string of a predetermined amount, quantities for a predetermined number of individual symbol values included in a symbol sting encoded from the bit string of the predetermined amount. The processor configured to specify positions of symbols in the symbol string for the individual symbol values from the quantities for the individual symbol values and a first parameter related to a number of arrangement patterns of the symbols that corresponds to the quantities for the individual symbol values. The processor configured to generate the symbol string by assigning to the specified positions the corresponding symbol values.

Abstract: A method includes assigning a symbol corresponding to a value of each of bit strings in a frame among the symbols in a constellation of a multi-level modulation scheme, to bit strings, converting a value of each of the bit strings other than a first bit string such that a symbol closer to a center of the constellation is assigned more among symbols, generating a error correction code for correcting an error of bit strings to insert the error correction code into the first bit string, generating the first error correction code from the bit strings other than the first bit string among bit strings, in a first period in which the error correction code is inserted into the first bit string in a period of the frame, and generating the error correction code from a second bit string in another second period in the period of the frame.

Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.

Abstract: An encoding device includes a processor. The processor configured to determine, based on an integer value that corresponds to a bit string of a predetermined amount, quantities for a predetermined number of individual symbol values included in a symbol sting encoded from the bit string of the predetermined amount. The processor configured to specify positions of symbols in the symbol string for the individual symbol values from the quantities for the individual symbol values and a first parameter related to a number of arrangement patterns of the symbols that corresponds to the quantities for the individual symbol values. The processor configured to generate the symbol string by assigning to the specified positions the corresponding symbol values.

Abstract: A communication device that generates a modulated signal with 32 QAM includes a modulator, a first encoder and a second encoder. The modulator generates a modulated signal by mapping each symbol in a data frame that includes transmission data, a first code, and a second code to a signal point among 32 QAM signal points. The first encoder encodes the data by using a first coding scheme to generate the first code. The second encoder encodes, by using a second coding scheme, a bit string formed from one specified bit in five bits allocated to each symbol in the data frame to generate the second code. The modulator performs mapping such that each pair of signal points adjacent to each other are arranged are different from each other in terms of a value of the one specified bit among the five bits.

Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A method includes assigning a symbol corresponding to a value of each of bit strings in a frame among the symbols in a constellation of a multi-level modulation scheme, to bit strings, converting a value of each of the bit strings other than a first bit string such that a symbol closer to a center of the constellation is assigned more among symbols, generating a error correction code for correcting an error of bit strings to insert the error correction code into the first bit string, generating the first error correction code from the bit strings other than the first bit string among bit strings, in a first period in which the error correction code is inserted into the first bit string in a period of the frame, and generating the error correction code from a second bit string in another second period in the period of the frame.

Abstract: An optical communication apparatus includes a first monitor that monitors a first signal carried on a first polarization and outputs a first monitor value representing a transmission characteristic of the first signal, a second monitor that monitors a second signal carried on a second polarization orthogonal to the first polarization and outputs a second monitor value representing a transmission characteristic of the second signal, and a transmitting circuit that notifies a transmitting source of the first signal and the second signal of the first monitor value and the second monitor value.

Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.

Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.

Abstract: An optical transmission system includes a first optical transmission apparatus that adds a plurality of error correction codes to a main signal, retrieves, from a first error correction code that is added to the main signal and that corresponds to a first sub-carrier among the plurality of sub-carriers, a first code portion in excess of a predetermined redundancy level, distributes the first code portion to a second sub-carrier among the plurality of sub-carriers, concatenates a second code portion into the first error correction code, and transmits an optical signal including the main signal multiplexed with the first error correction code that has been concatenated with the second code portion.

Abstract: An error correction method of executing error correction for a coded signal using a space coupling LDPC, includes setting a column weight in a column direction of an element matrix that among element matrices of the space coupling LDPC, corresponds to one end side of a bit string of the signal, to be large as a parity check matrix for detecting errors in multiplying the signal.