Patents by Inventor Yohei Masamori

Yohei Masamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127655
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 21, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Publication number: 20210005627
    Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 7, 2021
    Inventors: Tatsuya HINOUE, Kengo KAJIWARA, Ryosuke ITOU, Naohiro HOSODA, Yohei MASAMORI, Kota FUNAYAMA, Keisuke TSUKAMOTO, Hirofumi WATATANI
  • Publication number: 20200286815
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Patent number: 10381443
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10115632
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yohei Masamori, Hiroyuki Ogawa
  • Publication number: 20180301374
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Yohei MASAMORI, Hiroyuki OGAWA
  • Publication number: 20180261671
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 10020363
    Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 10, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Patent number: 9985098
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Publication number: 20180122904
    Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
  • Publication number: 20180122905
    Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai