Patents by Inventor Yohei Matsumoto

Yohei Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9603788
    Abstract: An object of the present invention is to provide a hair styling composition formulated to make hair styling easy and to add wet-look shine to hair. The hair styling composition which achieves the above object contains (A) a thickener, (B) a hair fixative polymer and/or a liquid oil, (C) a wax particle dispersion, and (D) water. In the hair styling composition of the present invention, the wax particle dispersion (C) is preferably an Euphorbia Cerifera (Candelilla) wax particle dispersion or a beeswax particle dispersion, or preferably contains wax, at least one nonionic surfactant selected from the group consisting of polyoxyethylene cetyl ether and polyoxyethylene polyoxypropylene cetyl ether, and water.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 28, 2017
    Assignee: MILBON CO., LTD.
    Inventors: Marina Mimura, Yusuke Takino, Yohei Matsumoto
  • Publication number: 20170071843
    Abstract: A hair treatment agent in which penetrability of a modified peptide into the internal structure of the hair can be enhanced even under the conditions of acidic pH, and a method for causing a modified peptide to penetrate into the hair, are provided. Disclosed is a hair treatment agent at a pH of from 3.5 to 5.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 16, 2017
    Inventors: Yohei MATSUMOTO, Atsushi YAMADA, Naoto MATSUMOTO
  • Publication number: 20150147285
    Abstract: An object of the present invention is to provide a hair styling composition formulated to make hair styling easy and to add wet-look shine to hair. The hair styling composition which achieves the above object contains (A) a thickener, (B) a hair fixative polymer and/or a liquid oil, (C) a wax particle dispersion, and (D) water. In the hair styling composition of the present invention, the wax particle dispersion (C) is preferably an Euphorbia Cerifera (Candelilla) wax particle dispersion or a beeswax particle dispersion, or preferably contains wax, at least one nonionic surfactant selected from the group consisting of polyoxyethylene cetyl ether and polyoxyethylene polyoxypropylene cetyl ether, and water.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 28, 2015
    Inventors: Marina MIMURA, Yusuke TAKINO, Yohei MATSUMOTO
  • Patent number: 8537603
    Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: September 17, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Yohei Matsumoto, Hanpei Koike
  • Publication number: 20120120717
    Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
    Type: Application
    Filed: July 2, 2010
    Publication date: May 17, 2012
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Toshihiro Sekigawa, Yohei Matsumoto, Hanpei Koike
  • Patent number: 7886250
    Abstract: The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: February 8, 2011
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yohei Matsumoto, Hanpei Koike
  • Patent number: 7797664
    Abstract: With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 14, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yohei Matsumoto, Hanpei Koike
  • Patent number: 7768314
    Abstract: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: August 3, 2010
    Assignee: National University Corporation Okayama University
    Inventors: Yohei Matsumoto, Akira Masaki
  • Publication number: 20090009215
    Abstract: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes.
    Type: Application
    Filed: March 28, 2005
    Publication date: January 8, 2009
    Inventors: Yohei Matsumoto, Akira Masaki
  • Publication number: 20080282214
    Abstract: The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.
    Type: Application
    Filed: April 15, 2008
    Publication date: November 13, 2008
    Applicant: National Institute of Adv. Ind. Science and Tech.
    Inventors: Yohei Matsumoto, Hanpei Koike
  • Publication number: 20070300201
    Abstract: With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 27, 2007
    Applicant: National Inst of Adv Industrial Science and Tech.
    Inventors: Yohei MATSUMOTO, Hanpei Koike