Abstract: An object of the present invention is to provide a hair styling composition formulated to make hair styling easy and to add wet-look shine to hair. The hair styling composition which achieves the above object contains (A) a thickener, (B) a hair fixative polymer and/or a liquid oil, (C) a wax particle dispersion, and (D) water. In the hair styling composition of the present invention, the wax particle dispersion (C) is preferably an Euphorbia Cerifera (Candelilla) wax particle dispersion or a beeswax particle dispersion, or preferably contains wax, at least one nonionic surfactant selected from the group consisting of polyoxyethylene cetyl ether and polyoxyethylene polyoxypropylene cetyl ether, and water.

Abstract: A hair treatment agent in which penetrability of a modified peptide into the internal structure of the hair can be enhanced even under the conditions of acidic pH, and a method for causing a modified peptide to penetrate into the hair, are provided. Disclosed is a hair treatment agent at a pH of from 3.5 to 5.

Abstract: An object of the present invention is to provide a hair styling composition formulated to make hair styling easy and to add wet-look shine to hair. The hair styling composition which achieves the above object contains (A) a thickener, (B) a hair fixative polymer and/or a liquid oil, (C) a wax particle dispersion, and (D) water. In the hair styling composition of the present invention, the wax particle dispersion (C) is preferably an Euphorbia Cerifera (Candelilla) wax particle dispersion or a beeswax particle dispersion, or preferably contains wax, at least one nonionic surfactant selected from the group consisting of polyoxyethylene cetyl ether and polyoxyethylene polyoxypropylene cetyl ether, and water.

Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

Abstract: The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.

Abstract: With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.

Abstract: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes.

Abstract: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes.

Abstract: The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.

Abstract: With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.