Abstract: A driving circuit includes a first transistor outputting a drive signal, and a third transistor supplied with a reset signal. A source electrode of the first transistor is supplied with a first clock signal. A source electrode of the third transistor is supplied with a second clock signal. The second clock signal has a phase different from a phase of the first clock signal. The second clock signal has a voltage that remains at a high level for a time period from a start point to an end point within a time period throughout which a potential of a node is higher than a gate-on voltage of the third transistor. The start point is prior to a time point of supplying the reset signal. The end point falls between the time point of supplying the reset signal and a time point of stopping supplying the reset signal.

Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.

Abstract: A unit circuit of a gate drive circuit includes first to fourth transistors. The first transistor outputs a drive signal to a gate line. The second transistor is a transistor to which a set signal is inputted and which charges a node. The third transistor is a transistor to which a first reset signal is inputted and which discharges the node to a ground potential. The fourth transistor is a transistor to which a second reset signal supplied at a time point later than the first reset signal is inputted and which discharges the node to a gate-off voltage.

Abstract: An array substrate includes a transistor including a first electrode a semiconductor portion, a second electrode and a third electrode, a first insulating film provided on an upper-layer side of the first electrode and on a lower layer side of the semiconductor portion, a second insulating film provided on an upper-layer side of the second electrode and the third electrode, and a light reflective portion provided on an upper-layer side of the second insulating film, in which the second insulating film is provided with a first recessed portion at a position overlapping none of the first electrode and the semiconductor portion, the light reflective portion includes an overlapping portion overlapping the first electrode and the semiconductor portion and a non-overlapping portion overlapping none of the first electrode and the semiconductor portion, and the non-overlapping portion includes a first filling portion that fills the first recessed portion.

Abstract: A unit circuit of a gate drive circuit includes a transistor T2 that receives a set signal and a transistor T3 that receives a reset signal. At least one of the transistors T2 and T3 includes a first channel and a second channel. A length of the second channel is longer than a length of the first channel, or a width of the second channel is narrower than a width of the first channel, or mobility of a second semiconductor layer of the transistor T2 is lower than mobility of a first semiconductor layer of the transistor T2.

Abstract: A driving circuit includes a first transistor outputting a drive signal, and a third transistor supplied with a reset signal. A source electrode of the first transistor is supplied with a first clock signal. A source electrode of the third transistor is supplied with a second clock signal. The second clock signal has a phase different from a phase of the first clock signal. The second clock signal has a voltage that remains at a high level for a time period from a start point to an end point within a time period throughout which a potential of a node is higher than a gate-on voltage of the third transistor. The start point is prior to a time point of supplying the reset signal. The end point falls between the time point of supplying the reset signal and a time point of stopping supplying the reset signal.

Abstract: In a unit circuit constituting a shift register, as a constituent element for changing the potential of a node (first control node) connected to the gate terminal of an output control transistor from a high level to a low level, two thin film transistors (a first reset transistor and a second reset transistor) connected in series between the first control node and an input terminal for a low-level DC power supply voltage VSS are provided. A capacitor is provided between the drain terminal and the source terminal of each of the two thin film transistors.

Abstract: A scanning signal line drive circuit as a GDM circuit is composed of a plurality of cascade-connected unit circuits and is operated by a multi-phase clock signal in which pulses partially overlap. The nth stage unit circuit includes: an internal node; a diode-connected set transistor connected to a set input terminal; a reset transistor including a drain terminal connected to the internal node, a source terminal connected to a reset state voltage terminal, and a gate terminal connected to the reset input terminal; and an output circuit including an output transistor connected to a clock input terminal and a capacitor, a scanning signal G(n?2), a scanning signal G(n+2), and a scanning signal G(n+1) being supplied to the set input terminal, the reset input terminal, and the reset state voltage terminal, respectively.

Abstract: In a display device, a switching component includes a first electrode being a portion of a first conductive film, a semiconductor section being a portion of a semiconductor film disposed above the first conductive film via a first insulating film, a second electrode being a portion of a second conductive film disposed above the semiconductor film, and a third electrode being a portion of the second conductive film. A first line is a portion of a third conductive film disposed above the second conductive film via a second insulating film. A first terminal includes a first terminal portion being a portion of the second conductive film and a second terminal portion being a portion of the third conductive film. The second insulating film includes a contact hole overlapping the first line and the second electrode and a contact hole overlapping the first and second terminal portions.

Abstract: An array substrate includes a gate line, a source line crossing the gate line, a switching component disposed on a crossing portion of the gate line and the source line, a semiconductor film included in the switching component, a first insulating film disposed between a layer including the gate line and a layer including the semiconductor film, and a second insulating film disposed between a layer including the semiconductor film and a layer including the source line. The source line overlaps the gate line via the first insulating film and the second insulating film.

Abstract: A transistor includes a first electrode, a first semiconductor portion that is at least partly superimposed on the first electrode and that is composed of a semiconductor material, a first insulating film that is interposed between the first electrode and the first semiconductor portion, a second electrode that is superimposed on a part of the first semiconductor portion and that is connected to the first semiconductor portion, and a third electrode that is located in a layer in which the second electrode is located, that is superimposed on a part of the first semiconductor portion, and that is connected to the first semiconductor portion. An electric potential of the second electrode is lower than that of the third electrode. The third electrode includes a first portion that is spaced from the second electrode and a second portion that is spaced from the second electrode opposite the first portion.

Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.

Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.

Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.

Abstract: A transistor includes a first electrode, a first semiconductor portion that is at least partly superimposed on the first electrode and that is composed of a semiconductor material, a first insulating film that is interposed between the first electrode and the first semiconductor portion, a second electrode that is superimposed on a part of the first semiconductor portion and that is connected to the first semiconductor portion, and a third electrode that is located in a layer in which the second electrode is located, that is superimposed on a part of the first semiconductor portion, and that is connected to the first semiconductor portion. An electric potential of the second electrode is lower than that of the third electrode. The third electrode includes a first portion that is spaced from the second electrode and a second portion that is spaced from the second electrode opposite the first portion.

Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.