Patents by Inventor Yohei Yanagida
Yohei Yanagida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9293578Abstract: Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film.Type: GrantFiled: July 3, 2013Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Patent number: 8841724Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: GrantFiled: December 29, 2010Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Kenji Miyakoshi, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Publication number: 20140015049Abstract: An LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, and feeding regions of the first and second conduction types formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region is formed at a distance from the field oxide film in an end portion in a longitudinal direction, and desirably the feeding region is intermittently formed at given intervals in the longitudinal direction, and the feeding region is applied to the first semiconductor region.Type: ApplicationFiled: July 3, 2013Publication date: January 16, 2014Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Patent number: 8546213Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.Type: GrantFiled: December 7, 2010Date of Patent: October 1, 2013Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Patent number: 8525291Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: GrantFiled: June 13, 2012Date of Patent: September 3, 2013Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Publication number: 20120256291Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Yohei Yanagida
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Patent number: 8217425Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: GrantFiled: July 20, 2009Date of Patent: July 10, 2012Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
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Publication number: 20110278669Abstract: Disclosed is a high-voltage diode structure which realizes high reverse recovery capability and high maximum allowable forward current. The distance between a longitudinal end of a p well layer in an anode region and an element isolation region formed to surround the diode is 5 ?m or shorter so as to allow a depletion layer to reach the element isolation region when a maximum rated reverse voltage is applied. During reverse recovery, the electric field strength at an end portion of a p well layer is reduced, hole current is reduced, and local temperature rises are reduced.Type: ApplicationFiled: May 11, 2011Publication date: November 17, 2011Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Takayuki Oshima, Yohei Yanagida, Takahiro Fujita
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Publication number: 20110215401Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.Type: ApplicationFiled: December 29, 2010Publication date: September 8, 2011Applicant: Hitachi, Ltd.Inventors: Kenji MIYAKOSHI, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
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Publication number: 20110140199Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.Type: ApplicationFiled: December 7, 2010Publication date: June 16, 2011Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Yohei Yanagida
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Publication number: 20100078676Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.Type: ApplicationFiled: July 20, 2009Publication date: April 1, 2010Inventors: Tomoyuki MIYOSHI, Shinichiro WADA, Yohei YANAGIDA