Patents by Inventor Yohei YASUDA

Yohei YASUDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11211905
    Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 28, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yohei Yasuda, Hidefumi Kushibe, Toshihiro Yagi
  • Patent number: 11152902
    Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Patent number: 11074948
    Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Publication number: 20200412310
    Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Publication number: 20200349989
    Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Patent number: 10819295
    Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 27, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Patent number: 10762937
    Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Publication number: 20200266774
    Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.
    Type: Application
    Filed: August 28, 2019
    Publication date: August 20, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yohei YASUDA, Hidefumi KUSHIBE, Toshihiro YAGI
  • Publication number: 20200266783
    Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.
    Type: Application
    Filed: August 30, 2019
    Publication date: August 20, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei YASUDA
  • Patent number: 10665274
    Abstract: A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Publication number: 20200035277
    Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 30, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei YASUDA
  • Patent number: 10535385
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Tsuji, Hiroki Ohkouchi, Shota Note, Masashi Nakata, Yohei Yasuda
  • Publication number: 20190348093
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro TSUJI, Hiroki OHKOUCHI, Shota NOTE, Masashi NAKATA, Yohei YASUDA
  • Publication number: 20190287580
    Abstract: A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.
    Type: Application
    Filed: August 29, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei YASUDA
  • Patent number: 10403341
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Tsuji, Hiroki Ohkouchi, Shota Note, Masashi Nakata, Yohei Yasuda
  • Publication number: 20190080734
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro TSUJI, Hiroki OHKOUCHI, Shota NOTE, Masashi NAKATA, Yohei YASUDA
  • Patent number: 9679617
    Abstract: According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 13, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yohei Yasuda, Hiromitsu Komai, Kensuke Yamamoto, Masaru Koyanagi, Yasuhiro Hirashima
  • Publication number: 20170084313
    Abstract: According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.
    Type: Application
    Filed: June 14, 2016
    Publication date: March 23, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yohei YASUDA, Hiromitsu KOMAI, Kensuke YAMAMOTO, Masaru KOYANAGI, Yasuhiro HIRASHIMA