Abstract: An improved carpeting gate array having a plurality of basic cells (9) each comprising an N channel MOS transistor (8) and a P channel MOS transistor (7) continuously arranged in row and column directions comprises a logic cell region (20) comprising a plurality of basic cells (9) continuously formed in a channel width direction (a direction intersecting with a direction in which their gate electrodes (4) of a plurality of N channel or P channel MOS transistors are continuously arranged spaced apart from each other), and an interconnection region (21) for providing interconnections to the logic cells (20) continuously formed in the channel width direction. The size in a width direction of the interconnection region is defined by the size in a channel length direction (a direction intersecting with the channel width direction) of the basic cells (9).