Patents by Inventor Yohichi Okumura
Yohichi Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415190Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).Type: GrantFiled: August 16, 2011Date of Patent: April 9, 2013Assignee: Texas Instruments IncorporatedInventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Patent number: 8390032Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.Type: GrantFiled: October 14, 2011Date of Patent: March 5, 2013Assignee: Texas Instruments IncorporatedInventors: Yohichi Okumura, Josef Muenz
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Publication number: 20120032270Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.Type: ApplicationFiled: October 14, 2011Publication date: February 9, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yohichi Okumura, Josef Muenz
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Publication number: 20110300666Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).Type: ApplicationFiled: August 16, 2011Publication date: December 8, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Patent number: 7999293Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).Type: GrantFiled: June 29, 2010Date of Patent: August 16, 2011Assignee: Texas Instruments IncorporatedInventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Publication number: 20100258895Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).Type: ApplicationFiled: June 29, 2010Publication date: October 14, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Patent number: 7745857Abstract: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the main surface of the first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) formed at least on the second semiconductor layer separate the device into the regions of plural photodiodes (PD1-PD4). Conductive layer 18 is formed on the second semiconductor layer 16 in a pattern that is divided for each of the photodiodes and is connected to the second semiconductor layer 16 along the outer periphery with respect to all of the plural photodiodes. Insulation layer (19, 21) is formed on the entire surface to cover conductive layer 18.Type: GrantFiled: March 29, 2006Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Publication number: 20090072314Abstract: The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yohichi Okumura, Josef Muenz
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Publication number: 20060220076Abstract: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the main surface of the first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) formed at least on the second semiconductor layer separate the device into the regions of plural photodiodes (PD1-PD4). Conductive layer 18 is formed on the second semiconductor layer 16 in a pattern that is divided for each of the photodiodes and is connected to the second semiconductor layer 16 along the outer periphery with respect to all of the plural photodiodes. Insulation layer (19, 21) is formed on the entire surface to cover conductive layer 18.Type: ApplicationFiled: March 29, 2006Publication date: October 5, 2006Inventors: Yohichi Okumura, Hiroyuki Tomomatsu
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Patent number: 6355578Abstract: To offer a technique that can form electrodes in a composite device without using a lift-off method. In the manufacture of a composite device 2 in which a wafer 50 that has a sacrificial layer 51 is used, a mask film 66 that has been patterned is formed; patterning is given to a structural layer 54, the sacrificial layer 51 is etched from the area that is exposed, a movable part 11 is formed in an area where said sacrificial layer 51 is removed, and a fixed part 10 is formed in an area where the sacrificial layer 51 remains; also, a thin metallic film 60 is formed and patterning is given before forming the mask film 66, with electrodes 37 for an external electrical connection being formed. A protective film thin titanium tungsten film 64 is formed on the surface of said thin metallic film 60, with the thin metallic film 60 being protected during etching of the sacrificial layer 51.Type: GrantFiled: October 27, 1998Date of Patent: March 12, 2002Assignee: Texas Instruments IncorporatedInventor: Yohichi Okumura