Abstract: In order to facilitate traffic offload to small base stations, the base station includes a neighboring cell list including information on other base stations around the base station and a neighboring base station information management means which manages the neighboring cell list, and which, based on a criterion that is different depending on whether a base station included in the neighboring cell list is a small base station having a subordinate small cell or a non-small base station, deletes information on the base station included in the neighboring cell list from the neighboring cell list at a predetermined frequency.

Abstract: A radio communication system, in a base station apparatus, previously registers neighboring base station information as a part of base station management information, and informs the terminal station of the neighboring base station information. The base station apparatus includes a handover processing unit for detecting that the terminal station has implemented handover that does not pass through a handover preparation phase from an other base station that has not been registered in a list of the neighboring base station information; and a management unit for dynamically additionally registering the other base station in the list of the neighboring base station information when implementation of the handover has been detected by the handover processing unit.

Abstract: An error diffusion processing circuit includes a memory having a predetermined size in which (P?1)×M dithering threshold matrices in a predetermined size for each of the quantization thresholds and color components are pre-stored, and a quantization threshold selector configured to select (P?1) matrices for the color component of the target pixel data from the dithering threshold matrices stored in the memory, and read an element from the elements of the selected matrices in accordance with a pixel position of the target pixel data in the image data for output as the (P?1) quantization thresholds. P is an integer of 2 or more and M is a positive integer. The data size of the dithering threshold matrices is set to be equal to or less than a value obtained by dividing a size of the memory by the number of dithering threshold matrices.

Abstract: A radio communication system, in a base station apparatus, previously registers neighboring base station information as a part of base station management information, and informs the terminal station of the neighboring base station information. The base station apparatus includes a handover processing unit for detecting that the terminal station has implemented handover that does not pass through a handover preparation phase from an other base station that has not been registered in a list of the neighboring base station information; and a management unit for dynamically additionally registering the other base station in the list of the neighboring base station information when implementation of the handover has been detected by the handover processing unit.

Abstract: A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit.

Abstract: An error diffusion processing circuit includes a memory having a predetermined size in which (P?1)×M dithering threshold matrices in a predetermined size for each of the quantization thresholds and color components are pre-stored, and a quantization threshold selector configured to select (P?1) matrices for the color component of the target pixel data from the dithering threshold matrices stored in the memory, and read an element from the elements of the selected matrices in accordance with a pixel position of the target pixel data in the image data for output as the (P?1) quantization thresholds. P is an integer of 2 or more and M is a positive integer. The data size of the dithering threshold matrices is set to be equal to or less than a value obtained by dividing a size of the memory by the number of dithering threshold matrices.

Abstract: A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.

Abstract: A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit.

Abstract: Disclosed is a transmitter/receiver which performs transmitting and receiving operations based on CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) system. The transmitter/receiver includes a first unit, a second unit and a DC offset control unit. The first unit obtains a DC offset value generated in the transmitter/receiver and holds the obtained DC offset value. The second unit removes the held DC offset value from received data. The DC offset control unit causses the first unit to operate upon response to at least one of transmission completion and reception completion.

Abstract: A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.

Abstract: Disclosed is a transmitter/receiver which performs transmitting and receiving operations based on CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) system. The transmitter/receiver includes a first unit, a second unit and a DC offset control unit. The first unit obtains a DC offset value generated in the transmitter/receiver and holds the obtained DC offset value. The second unit removes the held DC offset value from received data. The DC offset control unit causses the first unit to operate upon response to at least one of transmission completion and reception completion.