Abstract: In a right PI layer inclined area, a photosensitive PI layer covering an underlying PI layer exposed from an inorganic film of a moisture-proof layer, a gate insulating layer, a second insulating layer, and a third insulating layer is formed.

Abstract: In formation of a gate electrode, a metal film forming a gate electrode of TFT is formed on a gate insulating film covering a semiconductor layer having an island shape, the gate electrode is formed on the metal film by dry etching, and the exposed gate electrode is subjected to a plasma treatment using oxygen or nitrogen. This prevents formation of needle-shaped or granular crystal while a reduction in production efficiency is suppressed.

Abstract: At a bending section of a frame region, an insulating film with a groove formed on a front surface of the insulating film is provided, the groove extending in a direction intersecting one side of a display region on a terminal section side, and a frame wiring line is provided, at the bending section, to be bent to intersect the groove between the insulating film and a protection film.

Abstract: A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etching the conductive film 51 and forming a source conductive film 46S connected to the semiconductor film 42 and a drain conductive film 46D connected to the semiconductor film 42, a resist forming process performed after the first etching process and forming a resist 53R covering the semiconductor film 42, the source conductive film 46S, and the drain conductive film 46D, and a second etching process performed after the resist forming process and performing etching for removing the conductive film 51 while using the resist 53R as a mask.

Abstract: A flexible organic EL display device includes a polycrystalline silicon layer in which an extent of alignment of a silicon crystal orientation by electron back scatter diffraction patterns with a 001 plane is greater than or equal to 3.

Abstract: In a part of a frame region defined around a display region, an insulating film having a slit formed on a front surface of the insulating film to extend in a direction intersecting an edge of the display region is provided, and a frame wiring line connected to a light-emitting element of the display region is provided, on the insulating film, to be bent to stride across the slit.

Abstract: A photosensitive PI layer fills a bending region and is formed on a third insulating layer in a display region and a terminal region. An opening is formed in the photosensitive PI layer while exposing a gate electrode extension wiring line. A contact hole is formed in a second insulating layer and the third insulating layer.

Abstract: In formation of a gate electrode, a second metal film is formed on a first metal film by adding oxygen or nitrogen in an inert gas atmosphere, the first metal film and the second metal film are patterned and subjected to a plasma treatment using oxygen or nitrogen, to form a third metal film. Thus, a gate electrode is formed. This prevents formation of needle-shaped or granular crystal while a reduction in production efficiency is suppressed.

Abstract: At a bending section of a frame region, an opening portion is formed on at least one layer of inorganic film included in a TFT layer, in which a residual layer of the inorganic film is formed, a flattening film is provided to plug the opening portion, and the frame wiring line is provided on the flattening film.

Abstract: The frame wiring line provided in a frame region includes, at a bending section, a plurality of branch wiring lines being divided into a plurality of branches, wherein the plurality of branch wiring lines are arranged at at least two types of heights relative to a resin substrate.

Abstract: An active matrix substrate (1001) includes a connecting portion (101). The connecting portion. (101) includes a lower conductive layer supported by a substrate; a first insulating layer formed so as to cover the lower conductive layer (2) and having a contact hole (6p) that exposes a part of the lower conductive layer (2); a bottom conductive film (4) that is disposed in the contact hole (6p) and covers at least a part of the exposed part of the lower conductive layer (2), the exposed part being exposed by the contact hole (6p); a second insulating layer (9) that is formed on the first insulating layer (6) and in the contact hole (6p), is in contact with the bottom conductive film (4) in the contact hole (6p), and has an opening (9p) that exposes a part of the bottom conductive film (4); and an upper conductive layer (8) that is disposed on the second insulating layer (9) and in the opening (9p) and is in contact with the bottom conductive film (4) in the opening (9p).

Abstract: An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93). The lower electrode is connected to a source electrode (4) via a contact hole provided in the passivation film and the planarizing film. No photoelectric conversion layer is provided directly above the contact hole.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer.

Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: A method of producing a semiconductor device according to an embodiment of the present invention includes: step (C) of forming an oxide semiconductor layer of a plurality of thin film transistors on a gate dielectric layer; step (F) of forming an aperture in an interlevel dielectric layer, the aperture being located between an active region and a plurality of terminal portions and extending through the interlevel dielectric layer; and step (G) of, after step (F), forming an upper conductive portion on the interlevel dielectric layer. In step (C), a protection layer made of the same oxide semiconductor film as the oxide semiconductor layer is formed above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions. In step (F), the aperture is formed so as to overlap the protection layer.

Abstract: A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etching the conductive film 51 and forming a source conductive film 46S connected to the semiconductor film 42 and a drain conductive film 46D connected to the semiconductor film 42, a resist forming process performed after the first etching process and forming a resist 53R covering the semiconductor film 42, the source conductive film 46S, and the drain conductive film 46D, and a second etching process performed after the resist forming process and performing etching for removing the conductive film 51 while using the resist 53R as a mask.

Abstract: A thin film transistor (TFT) 11 includes a gate electrode 11a, a channel section 11d formed of an oxide semiconductor film 17, a source electrode 11b connected to one end of the channel section 11d, and a drain electrode 11c connected to another end of the channel section 11d, and the oxide semiconductor film 17 is an oxide semiconductor containing at least gallium and indium and an atomic ratio Ga/(Ga+In) is from 1/4.2 to 1/3.3.

Abstract: A semiconductor device includes: a first thin film transistor (101) including a crystalline silicon semiconductor layer (13); and a second thin film transistor (102) including an oxide semiconductor layer (23).