Abstract: A gain switching determination circuit (250) compares/determines a comparative input voltage (Vc) from an inter-stage buffer (230) with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (210, 220), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A gain switching determination circuit (250) compares/determines a comparative input voltage (Vc) from an inter-stage buffer (230) with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (210, 220), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.

Abstract: The present invention has been achieved to provide a novel optical transmission system realizing high-speed optical transmission over greater distance by suppressing waveform degradation caused by mode dispersion and mode transition in a multimode optical transmission line. The optical transmission system of the present invention includes: an optical transmitter for transmitting incoherent light; an excitation mechanism for exciting a predetermined mode in the incoherent light transmitted from the optical transmitter; a multimode optical transmission line for transmitting the incoherent light transmitted from the excitation mechanism; a transmission mechanism for transmitting a predetermined mode in the incoherent light transmitted from the excitation mechanism; and an optical receiver for receiving the incoherent light transmitted from the transmission mechanism or the incoherent light transmitted from the transmission mechanism.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.