Abstract: A method of rewriting a flash EEPROM of an electronic control device for controlling a vehicle equipment via a microcomputer is proposed. The flash EEPROM stores a control program and a flash EEPROM rewriting program. The operation of the vehicle equipment is changed by changing the control program via a microcomputer. When receiving a control-program-rewriting command signal, data on an internal condition and state of connection of the microcomputer are memorized. Then, the control program is changed to the flash EEPROM rewriting program, so that the data are read according to the flash EEPROM rewriting program to control the microcomputer to operate in the same internal condition and state of connection thereof as before. Thereafter, the microcomputer rewrites the flash EEPROM with a new control program sent from outside. Therefore, the vehicle equipment can be continuously operated by a user during the rewriting mode.

Abstract: In an electronic control system, it is determined whether leading end identification information in a data verification space of a flash EEPROM of an electronic control unit is an expected value. When it is yes, it is then determined whether terminal identification information in the data verification space is the expected value. Then, when it is yes, it is determined whether the leading end identification information and the trailing end identification information are identical to each other. When it is yes, it is determined that data between the leading end identification information and the trailing end identification information is valid. Otherwise, it is determined that the data is invalid.

Abstract: A method of rewriting a flash EEPROM of an electronic control device for controlling a vehicle equipment via a microcomputer is proposed. The flash EEPROM stores a control program and a flash EEPROM rewriting program. The operation of the vehicle equipment is changed by changing the control program via a microcomputer. When receiving a control-program-rewriting command signal, data on an internal condition and state of connection of the microcomputer are memorized. Then, the control program is changed to the flash EEPROM rewriting program, so that the data are read according to the flash EEPROM rewriting program to control the microcomputer to operate in the same internal condition and state of connection thereof as before. Thereafter, the microcomputer rewrites the flash EEPROM with a new control program sent from outside. Therefore, the vehicle equipment can be continuously operated by a user during the rewriting mode.

Abstract: A microcomputer comprises an intermittent operation control section for intermittently operating a CPU. Moreover, the microcomputer comprises a timer block, a level detecting circuit or a timer interlocking control section as the circuits for assisting operation of the CPU. The CPU realizes a timer function with the timer block. The CPU can start the process in response to a level of an external signal with the level detecting circuit. The CPU can start operation with the timer interlocking control section after an external apparatus is driven. With the structure explained above, power consumption of the microcomputer is reduced.

Abstract: A first receiving message is stored in a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and thereafter transferred directly to a RAM by a DMA controller. The number of times of transfer operation is restricted with an upper limit value. The CPU does not read the second receiving message from the message box but from the RAM and executes the processes based on the message. Generation of failure in the receiving data fetching processes is reduced without physical expansion of the storage regions of the message box.

Abstract: A first receiving message is stored into a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and thereafter transferred in direct to a RAM by a DMA controller. The number of times of transfer operation is restricted with an upper limit value. The CPU does not read the second receiving message from the message box but from the RAM and executes the processes based on the message. Generation of failure in the receiving data fetching processes is reduced without physical expansion of the storage regions of the message box.

Abstract: A microcomputer comprises an intermittent operation control section for intermittently operating a CPU. Moreover, the microcomputer comprises a timer block, a level detecting circuit or a timer interlocking control section as the circuits for assisting operation of the CPU. The CPU realizes a timer function with the timer block. The CPU can start the process in response to a level of an external signal with the level detecting circuit. The CPU can start operation with the timer interlocking control section after an external apparatus is driven. With the structure explained above, power consumption of the microcomputer is reduced.