Patents by Inventor Yoichi Fukushima
Yoichi Fukushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11038038Abstract: Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.Type: GrantFiled: August 13, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Yoichi Fukushima, Takuya Imamoto
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Publication number: 20210050428Abstract: Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.Type: ApplicationFiled: August 13, 2019Publication date: February 18, 2021Applicant: Micron Technology , Inc.Inventors: Yoichi Fukushima, Takuya Imamoto
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Patent number: 10763265Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.Type: GrantFiled: October 16, 2019Date of Patent: September 1, 2020Assignee: Micron Technology, Inc.Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
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Publication number: 20200083230Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.Type: ApplicationFiled: October 16, 2019Publication date: March 12, 2020Applicant: Micron Technology, Inc.Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
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Patent number: 10535665Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.Type: GrantFiled: September 7, 2018Date of Patent: January 14, 2020Assignee: Micron Technology, Inc.Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
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Patent number: 9385130Abstract: In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.Type: GrantFiled: January 25, 2012Date of Patent: July 5, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Yoichi Fukushima
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Publication number: 20160086956Abstract: One semiconductor device has a groove formed on one surface of a semiconductor substrate, a gate electrode formed on the lower part of the groove with a gate insulation film interposed there between, a side wall insulation film made of a nitride film formed on the inner wall of the groove above the gate electrode, and an embedded insulation film formed in the groove enclosed by the side wall insulation film above the gate electrode. The side wall insulation film is shaped so that the width increases closer the bottom part of the groove.Type: ApplicationFiled: April 16, 2014Publication date: March 24, 2016Inventor: Yoichi Fukushima
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Patent number: 8427393Abstract: The multi-layer display device apparatus has a first display part, a second display part arranged at the rear-side of the first display part, a transforming part arranged between the first and the second display part. The transforming part transforms a linear polarized light in to a non-polarized light. Further, the display device has a storage part which stores a parameter for adjusting the image quality of the image displayed on the first and second display part, and an image adjustment part which adjusts the image quality of the image displayed in the first and second display part based on the parameter stored in the storage part.Type: GrantFiled: March 4, 2011Date of Patent: April 23, 2013Assignee: SANYO Electric Co., Ltd.Inventors: Yasuhiko Nakazaki, Yoshinori Saito, Tsutomu Fujita, Yoichi Fukushima
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Publication number: 20130075824Abstract: A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions.Type: ApplicationFiled: May 10, 2012Publication date: March 28, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Yoichi FUKUSHIMA, Mika NISHISAKA
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Publication number: 20120193696Abstract: In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.Type: ApplicationFiled: January 25, 2012Publication date: August 2, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Yoichi FUKUSHIMA
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Publication number: 20120171178Abstract: The present invention relates to a nutritional composition, in particular directed to children of 3-6 years, said nutritional composition comprising a protein source, a source of available carbohydrates, a lipid source, at least one probiotic microorganism, and prebiotics, wherein said lipid source comprises DHA (docosahexaenoic acid) and/or ARA (arachidonic acid). The nutritional composition improves cognitive performance, in particular memory, learning comprehension, alertness, attention, concentration, processing speed, conceptual thinking, abstract thinking, verbal abilities, language comprehension, psychomotor skills, curiosity, and confident interaction with the environment. Preferably, the composition comprises one, a combination of several or all selected of the group of DHA, ARA, LA, ALA, choline, iron, iodine and folic acid.Type: ApplicationFiled: June 1, 2010Publication date: July 5, 2012Applicant: NESTEC S.A.Inventors: Mathilde Fleith, Yoichi Fukushima, Gertrude Rapinett, Johannes Schmitt, Maria-Luiza Mateus
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Publication number: 20120171177Abstract: The present invention relates to a nutritional composition, in particular directed to toddlers and/or a weaning child, said nutritional composition comprising a protein source, a source of available carbohydrates, a lipid source, at least one probiotic microorganism, and prebiotics, wherein said lipid source comprises DHA (docosahexaenoic acid). The nutritional composition improves cognitive performance, in particular learning and memory of the child. Preferably, the composition comprises iron, zinc, vitamin D and/or sialic acid. Preferably, the composition comprises a source of phospholipids rich in DHA.Type: ApplicationFiled: June 1, 2010Publication date: July 5, 2012Applicant: NESTEC S.A.Inventors: Jan Biehl, Frederic Destaillats, Laurent Fay, Yoichi Fukushima, Johannes Schmitt, Bing Wang
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Patent number: 8193063Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second gate electrodes are formed over a semiconductor substrate. An epitaxial layer is selectively formed over the semiconductor substrate. The epitaxial layer is adjacent to the first gate electrode. A first impurity is introduced into the semiconductor substrate through the epitaxial layer to form a first impurity region and directly into the semiconductor substrate to form a second impurity region. The first and second impurity regions are adjacent to the first and second gate electrodes, respectively. The first impurity region includes the epitaxial layer. A first bottom surface of the first impurity region is shallower in level than a second bottom surface of the second impurity region.Type: GrantFiled: June 8, 2010Date of Patent: June 5, 2012Assignee: Elpida Memory, Inc.Inventor: Yoichi Fukushima
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Publication number: 20110268702Abstract: The present invention generally relates to the field of obesity and/or metabolic disorders. In particular the present invention relates to the use of probiotics to treat obesity and/or metabolic disorders. One embodiment of the present invention relates to the use of Lactobacillus paracasei, in particular Lactobacillus paracasei ST11, for the preparation of a composition to treat or prevent metabolic disorders.Type: ApplicationFiled: May 14, 2009Publication date: November 3, 2011Applicant: NESTEC S.A.Inventor: Yoichi Fukushima
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Publication number: 20110215991Abstract: The multi-layer display device apparatus has a first display part, a second display part arranged at the rear-side of the first display part, a transforming part arranged between the first and the second display part. The transforming part transforms a linear polarized light in to a non-polarized light. Further, the display device has a storage part which stores a parameter for adjusting the image quality of the image displayed on the first and second display part, and an image adjustment part which adjusts the image quality of the image displayed in the first and second display part based on the parameter stored in the storage part.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Applicants: SANYO ELECTRIC CO., LTD., SANYO ELECTRIC SYSTEM SOLUTIONS CO., LTD.Inventors: Yasuhiko NAKAZAKI, Yoshinori SAITO, Tsutomu FUJITA, Yoichi FUKUSHIMA
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Publication number: 20110151656Abstract: A method of forming a semiconductor device, the method including the following processes. A groove is formed in a semiconductor substrate. A gate electrode is formed in the groove. A boron-phosphorus silicate glass film is formed over the gate electrode. An etching process is performed using the boron-phosphorus silicate glass film as an etching stopper for preventing the gate electrode from being removed.Type: ApplicationFiled: December 8, 2010Publication date: June 23, 2011Applicant: Elpida Memory, Inc.Inventor: Yoichi FUKUSHIMA
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Publication number: 20100323484Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second gate electrodes are formed over a semiconductor substrate. An epitaxial layer is selectively formed over the semiconductor substrate. The epitaxial layer is adjacent to the first gate electrode. A first impurity is introduced into the semiconductor substrate through the epitaxial layer to form a first impurity region and directly into the semiconductor substrate to form a second impurity region. The first and second impurity regions are adjacent to the first and second gate electrodes, respectively. The first impurity region includes the epitaxial layer. A first bottom surface of the first impurity region is shallower in level than a second bottom surface of the second impurity region.Type: ApplicationFiled: June 8, 2010Publication date: December 23, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Yoichi FUKUSHIMA
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Patent number: 7585736Abstract: A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride film in a first region while leaving said first insulating film and said nitride film in a second region. The step (c) is a step of forming a second insulating film on said semiconductor substrate in said first region. Here, a thickness of said second insulating film is different from that of said first insulating film. A third insulating film is formed on said nitride film in said second region along with the formation of said second insulating film. The step (d) is a step of removing said third insulating film and said nitride film in said second region.Type: GrantFiled: March 16, 2007Date of Patent: September 8, 2009Assignee: Elpida Memory, Inc.Inventor: Yoichi Fukushima
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Publication number: 20070218666Abstract: A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride film in a first region while leaving said first insulating film and said nitride film in a second region. The step (c) is a step of forming a second insulating film on said semiconductor substrate in said first region. Here, a thickness of said second insulating film is different from that of said first insulating film. A third insulating film is formed on said nitride film in said second region along with the formation of said second insulating film. The step (d) is a step of removing said third insulating film and said nitride film in said second region.Type: ApplicationFiled: March 16, 2007Publication date: September 20, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Yoichi Fukushima
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Patent number: 5292616Abstract: A technique of an optical card having high information recording density. A specially superior writing characteristic is required for an additional recording optical card among optical cards. In the case where the optical card of additional recording type is closed, reduction in the writing characteristic is observed. In this invention, a sensitizing layer (50), which serves as escape for molten recording material at writing, is provided in rear of an optical recording section (30), so that an optical card is produced which is superior in both environmental resistance and writing ability. The sensitizing layer (50) is made of self-oxidizable or thermoplastic resin and an absorbing agent dispersed in the resin. The absorbing agent cooperates with the resin not only to improve a writing characteristic, but also to improve design ability and reading ability of the card.Type: GrantFiled: February 12, 1991Date of Patent: March 8, 1994Assignee: Kyodo Printing Co., Ltd.Inventors: Minoru Fujita, Yuji Kakinuma, Yoichi Fukushima