Patents by Inventor Yoichi Goto

Yoichi Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076596
    Abstract: A cell culture container includes: an insert member having a membrane on which a cell is seeded, the insert member defining a first inner space that functions as an anaerobic chamber; a container having an attachment/detachment portion to and from which the insert member is attachable and detachable, the container defining a second inner space that functions as an aerobic chamber; a sealing member that closes an opening of the aerobic chamber between the attachment/detachment portion and the insert member with the insert member being attached to the attachment/detachment portion; and a transfer mechanism that transfers force to the sealing member. The sealing member closes the opening in response to an input of the force from the transfer mechanism.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 7, 2024
    Inventors: Tsunehiro INOUE, Toyoyuki HASHIMOTO, Yasuko YONEDA, Kenji TAKUBO, Yoichi FUJIYAMA, Tomoki OHKUBO, Eiichi OZEKI, Ryogo TAKAI, Hiroomi GOTO, Sadamu TOMITA
  • Publication number: 20230352217
    Abstract: A resistor includes a resistive element, an insulation plate, a protective film, and a pair of electrodes. The resistive element includes a first face and a second face arranged to face in opposite directions in a thickness direction. The insulation plate is on the first face, and the protective film on the second face. The electrodes are spaced apart in a first direction perpendicular to the thickness direction, and held in contact with the resistive element. Each electrode includes a bottom portion opposite to the insulation plate with respect to the resistive element in the thickness direction. Each bottom portion overlaps with a part of the protective film as viewed in the thickness direction. The resistor further includes a pair of intermediate layers spaced apart in the first direction. The intermediate layers are formed of a material electrically conductive and containing a synthetic resin. Each intermediate layer includes a cover portion covering a part of the protective film.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventor: Yoichi GOTO
  • Patent number: 11742115
    Abstract: A resistor includes a resistive element, an insulation plate, a protective film, and a pair of electrodes. The resistive element includes a first face and a second face arranged to face in opposite directions in a thickness direction. The insulation plate is on the first face, and the protective film on the second face. The electrodes are spaced apart in a first direction perpendicular to the thickness direction, and held in contact with the resistive element. Each electrode includes a bottom portion opposite to the insulation plate with respect to the resistive element in the thickness direction. Each bottom portion overlaps with a part of the protective film as viewed in the thickness direction. The resistor further includes a pair of intermediate layers spaced apart in the first direction. The intermediate layers are formed of a material electrically conductive and containing a synthetic resin. Each intermediate layer includes a cover portion covering a part of the protective film.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 29, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Yoichi Goto
  • Publication number: 20220093294
    Abstract: A resistor includes a resistive element, an insulation plate, a protective film, and a pair of electrodes. The resistive element includes a first face and a second face arranged to face in opposite directions in a thickness direction. The insulation plate is on the first face, and the protective film on the second face. The electrodes are spaced apart in a first direction perpendicular to the thickness direction, and held in contact with the resistive element. Each electrode includes a bottom portion opposite to the insulation plate with respect to the resistive element in the thickness direction. Each bottom portion overlaps with a part of the protective film as viewed in the thickness direction. The resistor further includes a pair of intermediate layers spaced apart in the first direction. The intermediate layers are formed of a material electrically conductive and containing a synthetic resin. Each intermediate layer includes a cover portion covering a part of the protective film.
    Type: Application
    Filed: January 28, 2020
    Publication date: March 24, 2022
    Inventor: Yoichi GOTO
  • Publication number: 20210259771
    Abstract: A light radiating device (1A) performs solidification or cauterization of a biological tissue (PL) by radiating a light beam (BM). A light source (10A) emits the light beam (BM). An optical waveguide (20A) is a member being provided with a reflection surface (21A) totally reflecting the light beam (BM) on an inner circumferential side wall, causing the light beam (BM) emitted from the light source (10A) to enter a part enclosed by the inner circumferential side wall from one end, and sending the light beam (BM) to the other end. A catoptric system (30A) reflects the light beam (BM) sent to the other end of the optical waveguide (20A) and condenses the light beam (BM) on the biological tissue (PL).
    Type: Application
    Filed: July 19, 2019
    Publication date: August 26, 2021
    Applicants: Neuroceuticals lnc., l-PEX lnc.
    Inventors: Kazuo SHIMIZU, Yoichi GOTO, Toshifumi MATSUMOTO, Shoichi KAWAMURA
  • Patent number: 10529643
    Abstract: A semiconductor device that reduces the deformation of a metal base due to pressure during transfer molding, to thereby suppress the occurrence of cracks in an insulating layer to achieve high electrical reliability. The semiconductor device includes: a metal member provided, on its lower surface, with a projection and a depression, and a projecting peripheral portion surrounding the projection and the depression and having a height greater than or equal to a height of the projection of the projection and the depression; an insulating layer formed on an upper surface of the metal member; a metal layer formed on an upper surface of the insulating layer; a semiconductor element joined to an upper surface of the metal layer; and a sealing resin to seal the semiconductor element, the metal layer, the insulating layer and the metal member.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kei Yamamoto, Hodaka Rokubuichi, Dai Nakajima, Kiyofumi Kitai, Yoichi Goto
  • Publication number: 20180261520
    Abstract: A semiconductor device that reduces the deformation of a metal base due to pressure during transfer molding, to thereby suppress the occurrence of cracks in an insulating layer to achieve high electrical reliability. The semiconductor device includes: a metal member provided, on its lower surface, with a projection and a depression, and a projecting peripheral portion surrounding the projection and the depression and having a height greater than or equal to a height of the projection of the projection and the depression; an insulating layer formed on an upper surface of the metal member; a metal layer formed on an upper surface of the insulating layer; a semiconductor element joined to an upper surface of the metal layer; and a sealing resin to seal the semiconductor element, the metal layer, the insulating layer and the metal member.
    Type: Application
    Filed: September 20, 2016
    Publication date: September 13, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kei YAMAMOTO, Hodaka ROKUBUICHI, Dai NAKAJIMA, Kiyofumi KITAI, Yoichi GOTO
  • Patent number: 9685399
    Abstract: A power semiconductor device is provided with a base plate thermally connected to the power semiconductor element for heat generated from the power semiconductor element to be conducted to heat radiation fins. An electrically conductive member fixed to the base plate is electrically conducted to the base plate and is connected to ground, and has projections fitted into notches provided in the electrically conductive member. By deforming the projections, the electrically conductive member is fixed to the base plate and electrical conduction can be secured. With this arrangement, noise radiated from the power semiconductor element is reduced and malfunction of the power semiconductor element is suppressed.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 20, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toru Kimura, Yoichi Goto, Kiyofumi Kitai
  • Publication number: 20160300785
    Abstract: Projections 35 provided in a base plate 22 are fitted into notches provided in an electrically conductive member 12, and then the base plate 22 is fixed to the electrically conductive member 12 by deforming the projections 35 and the electrically conductive member 12 is connected to earth ground, so that noise radiated from a power semiconductor element 21 is reduced and malfunction of the power semiconductor element 21 is suppressed.
    Type: Application
    Filed: December 5, 2013
    Publication date: October 13, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Toru Kimura, Yoichi Goto, Kiyofumi Kitai
  • Publication number: 20160238121
    Abstract: A rack belt includes: a toothed belt body that is made of resin or rubber and is adapted to move in an extending direction; a first core wire made of metal which is embedded in the belt body in a state of extending in the extending direction of the belt body; and a second core wire made of metal which is embedded in the belt body in a state of being wound around the first core wire.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 18, 2016
    Applicant: AISIN SEIKI KABUSHISIKI KAISHA
    Inventors: Yusuke KOKUBO, Yoichi GOTO, Mikiyasu FUJII
  • Patent number: 9262437
    Abstract: An example of the present invention is a storage system comprising a first real storage apparatus including a plurality of real resources. The first real storage apparatus includes: real resource groups allocated to a plurality of virtual storage apparatuses; first management information for associating virtual resource identifiers individually assigned to real resources in a namespace independently defined for each of the plurality of virtual storage apparatuses with real resource identifiers individually assigned to the real resources in a namespace defined for the first real storage apparatus; and a controller for receiving a command including a designation with a virtual resource identifier, converting the virtual resource identifier in the command into a real resource identifier with reference to the first management information, and processing the command with the converted real resource identifier.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 16, 2016
    Assignee: HITACHI, LTD.
    Inventors: Hirotaka Nakagawa, Hideo Saito, Nobuhito Mori, Tomohiro Kawaguchi, Abhishek Johri, Naoko Ikegaya, Yoichi Goto, Kunihiko Nashimoto, Akira Yamamoto
  • Patent number: 9052839
    Abstract: An example is a method of controlling a storage system for providing a virtual storage apparatus that includes virtual storage resources associated with real storage resources of real storage apparatus. It includes receiving a virtual storage resource control command of a predetermined type specifying a first virtual storage resource in the virtual storage apparatus and a second virtual storage resource associated with the first virtual storage resource; referring to management information for managing association relations between the virtual storage resources and the real storage resources, to identify a first real storage resource associated with the first virtual storage resource and a first real storage apparatus including the first real storage resource; and selecting a second real storage resource associated with the second virtual storage resource from real storage resources within the first real storage apparatus, or creating the second real storage resource within the first real storage apparatus.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: June 9, 2015
    Assignee: HITACHI, LTD.
    Inventors: Hideo Saito, Hirotaka Nakagawa, Yoichi Goto, Abhishek Johri, Tomohiro Kawaguchi, Kunihiko Nashimoto, Nobuhito Mori, Naoko Ikegaya, Akira Yamamoto
  • Publication number: 20140201438
    Abstract: An example is a method of controlling a storage system for providing a virtual storage apparatus that includes virtual storage resources associated with real storage resources of real storage apparatus. It includes receiving a virtual storage resource control command of a predetermined type specifying a first virtual storage resource in the virtual storage apparatus and a second virtual storage resource associated with the first virtual storage resource; referring to management information for managing association relations between the virtual storage resources and the real storage resources, to identify a first real storage resource associated with the first virtual storage resource and a first real storage apparatus including the first real storage resource; and selecting a second real storage resource associated with the second virtual storage resource from real storage resources within the first real storage apparatus, or creating the second real storage resource within the first real storage apparatus.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Applicant: HITACHI, LTD.
    Inventors: Hideo Saito, Hirotaka Nakagawa, Yoichi Goto, Abhishek Johri, Tomohiro Kawaguchi, Kunihiko Nashimoto, Nobuhito Mori, Naoko Ikegaya, Akira Yamamoto
  • Publication number: 20140195573
    Abstract: An example of the present invention is a storage system comprising a first real storage apparatus including a plurality of real resources. The first real storage apparatus includes: real resource groups allocated to a plurality of virtual storage apparatuses; first management information for associating virtual resource identifiers individually assigned to real resources in a namespace independently defined for each of the plurality of virtual storage apparatuses with real resource identifiers individually assigned to the real resources in a namespace defined for the first real storage apparatus; and a controller for receiving a command including a designation with a virtual resource identifier, converting the virtual resource identifier in the command into a real resource identifier with reference to the first management information, and processing the command with the converted real resource identifier.
    Type: Application
    Filed: January 7, 2013
    Publication date: July 10, 2014
    Applicant: HITACHI, LTD.
    Inventors: Hirotaka Nakagawa, Hideo Saito, Nobuhito Mori, Tomohiro Kawaguchi, Abhishek Johri, Naoko Ikegaya, Yoichi Goto, Kunihiko Nashimoto, Akira Yamamoto
  • Patent number: 8659147
    Abstract: A power semiconductor circuit device and a method for manufacturing the same, both of which are provided with: a base board on which at least a power semiconductor element is mounted; a resin which molds the base board and the power semiconductor element in a state where partial surfaces of the base board, including a base board surface opposite to a surface on which the power semiconductor element is mounted, are exposed; and a heat dissipating fin joined to the base board by a pressing force. A groove is formed in the base board at a portion to be joined to the heat dissipating fin, and the heat dissipating fin is joined by caulking to the groove.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: February 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Mitsui, Hiroyuki Yoshihara, Toru Kimura, Masao Kikuchi, Yoichi Goto
  • Publication number: 20140035122
    Abstract: A power semiconductor device includes: a mold unit that includes a power semiconductor element, a base plate, and a mold unit, the power semiconductor element being mounted on one surface of the base plate, a convex portion being formed on an other surface of the base plate, the convex portion including a plurality of grooves, the mold unit having a mold resin with which the power semiconductor element is sealed in such a manner as to expose the convex portion; a plurality of radiation fins inserted into the grooves, respectively, and fixedly attached to the base plate by swaging; and a metal plate that includes a opening into which the convex portion is inserted, the metal plate being arranged between the mold unit and the radiation fins with the convex portion inserted into the opening, wherein the metal plate includes a protrusion that protrudes from an edge of the opening and that digs into a side surface of the convex portion when the convex portion is inserted into the opening.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shigeyuki Nakazato, Yoichi Goto, Kiyofumi Kitai, Toru Kimura
  • Patent number: 8643171
    Abstract: A power semiconductor device includes: a mold unit that includes a power semiconductor element, a base plate, and a mold unit, the power semiconductor element being mounted on one surface of the base plate, a convex portion being formed on an other surface of the base plate, the convex portion including a plurality of grooves, the mold unit having a mold resin with which the power semiconductor element is sealed in such a manner as to expose the convex portion; a plurality of radiation fins inserted into the grooves, respectively, and fixedly attached to the base plate by swaging; and a metal plate that includes a opening into which the convex portion is inserted, the metal plate being arranged between the mold unit and the radiation fins with the convex portion inserted into the opening, wherein the metal plate includes a protrusion that protrudes from an edge of the opening and that digs into a side surface of the convex portion when the convex portion is inserted into the opening.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeyuki Nakazato, Yoichi Goto, Kiyofumi Kitai, Toru Kimura
  • Patent number: 8525285
    Abstract: A semiconductor device having a substrate including a photodiode; a resin layer formed on an upper surface of the substrate, the resin layer not covering a light receiving region of the photodiode, the resin layer including at least one groove surrounding the light receiving region; and a molding resin portion formed by mold-sealing the photodiode with the resin layer thereon so as not to cover the light receiving region.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 3, 2013
    Assignee: Sony Corporation
    Inventors: Shuji Yoneda, Masato Oishi, Tamotsu Shinohara, Shinji Watanabe, Koji Miyata, Seiji Fukae, Kenji Yamauchi, Yoichi Goto, Masakazu Baba
  • Publication number: 20120161271
    Abstract: A semiconductor device having a substrate including a photodiode; a resin layer formed on an upper surface of the substrate, the resin layer not covering a light receiving region of the photodiode, the resin layer including at least one groove surrounding the light receiving region; and a molding resin portion formed by mold-sealing the photodiode with the resin layer thereon so as not to cover the light receiving region.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 28, 2012
    Applicant: SONY CORPORATION
    Inventors: Shuji Yoneda, Masato Oishi, Tamotsu Shinohara, Shinji Watanabe, Koji Miyata, Seiji Fukae, Kenji Yamauchi, Yoichi Goto, Masakazu Baba
  • Patent number: 8153467
    Abstract: A method for manufacturing a semiconductor device, includes the steps of: forming a resin layer on an upper surface of a substrate including a photodiode such that the resin layer does not cover a light receiving region of the photodiode; forming at least one groove in the resin layer so as to surround the light receiving region; and subsequently mold-sealing the photodiode by loading the substrate into a mold and filling the mold with a molding resin.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 10, 2012
    Assignee: Sony Corporation
    Inventors: Shuji Yoneda, Masato Oishi, Tamotsu Shinohara, Shinji Watanabe, Koji Miyata, Seiji Fukae, Kenji Yamauchi, Yoichi Goto, Masakazu Baba