Patents by Inventor Yoichi Hijikata

Yoichi Hijikata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7114101
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: September 26, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 7100086
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 29, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 7065678
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 20, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Patent number: 7047443
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code of a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM> The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 16, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 6922795
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: July 26, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Publication number: 20050102579
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Application
    Filed: November 12, 2004
    Publication date: May 12, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Publication number: 20050097401
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code of a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM> The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 5, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Publication number: 20040153802
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Application
    Filed: December 2, 2003
    Publication date: August 5, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Publication number: 20040153812
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.
    Type: Application
    Filed: November 5, 2003
    Publication date: August 5, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Patent number: 6665821
    Abstract: The present invention provides a microcomputer that makes, it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: December 16, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Patent number: 6553506
    Abstract: An objective is to provide information processing device and electronic equipment that is capable of transferring data rapidly while using start-stop synchronization. A communication section (142) comprised within a microcomputer (140) comprises a frequency division circuit (146) that divides a BCLK signal to generate an SMC1 signal (a clock signal for sampling each bit of data sent by start-stop synchronization) and a send/receive circuit (144) for transmitting data based on SMC1. The communication section (142) supplies the BCLK signal to a debugging tool (150) as a signal for enabling a frequency division circuit (156) to generate another signal SMC2. A division ratio control section (158) changes a division ratio FD2 in accordance with the frequency of BCLK and transfers division ratio data to the communication section (142), and the division ratio control section (148) changes a division ratio FD1 in the frequency division circuit (146) based on this division ratio data.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 22, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yoichi Hijikata, Makoto Kudo