Patents by Inventor Yoichi Katsuki
Yoichi Katsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8364988Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: May 5, 2011Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Publication number: 20110208983Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: May 5, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yonetaro TOTSUKA, Koichiro ISHIBASHI, Hiroyuki MIZUNO, Osamu Nishii, Kunio UCHIYAMA, Takanori SHIMURA, Asako SEKINE, Yoichi KATSUKI, Susumu NARITA
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Patent number: 7958379Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: December 30, 2008Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Publication number: 20100005324Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: December 30, 2008Publication date: January 7, 2010Inventors: Yonetaro TOTSUKA, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 7475261Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: February 2, 2004Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 7289802Abstract: An acquisition section acquires trace information including a plurality of log information having information on contents and types of log information based on message information of test signals transmitted to a communication terminal and a series of reply signals from the communication terminals, and provides clock time information at which the respective message information have been acquired. The trace information including the plurality of log information, is displayed in predetermined formats. An indication bar display section displays an indication bar on which the plurality of log information are arranged in a time series based on the clock time at which the respective message information have been acquired. A log sequence display section displays a predetermined number of log information as log sequences having time stamps based on the clock time information at which the respective log information have been acquired, so as to be associated with the indication bar.Type: GrantFiled: February 28, 2005Date of Patent: October 30, 2007Assignee: Anritsu CorporationInventors: Shoichi Nakamura, Tsuyoshi Sato, Hiroyuki Tsuda, Tsutomu Tokuke, Hiroki Shiina, Takashi Sakamoto, Yoichi Katsuki
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Publication number: 20060270398Abstract: A trace information acquisition section acquires trace information including a plurality of log information which have information on contents and types of log information based on predetermined message information of each of a series of test signals transmitted to a communication terminal for being evaluated by a communication terminal test measuring instrument and a series of reply signals from the communication terminal for being evaluated received by the communication terminal test measuring instrument, and provides clock time information at which the respective message information have been acquired. A trace information display processing control section displays the trace information including the plurality of log information in predetermined formats.Type: ApplicationFiled: February 28, 2005Publication date: November 30, 2006Applicant: Anritsu CorporationInventors: Shoichi Nakamura, Tsuyoshi Sato, Hiroyuki Tsuda, Tsutomu Tokuke, Hiroki Shiina, Takashi Sakamoto, Yoichi Katsuki
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Publication number: 20040158756Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: February 2, 2004Publication date: August 12, 2004Applicant: Renesas Technology CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 6715090Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: May 20, 1999Date of Patent: March 30, 2004Assignee: Renesas Technology CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita