Patents by Inventor Yoichi Kawano

Yoichi Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117517
    Abstract: Disclosed is an Fe-based electroplated steel sheet including: a Si-containing cold-rolled steel sheet containing Si in an amount of 0.1 mass % or more and 3.0 mass % or less; and an Fe-based electroplating layer formed on at least one surface of the Si-containing cold-rolled steel sheet with a coating weight per surface of 5.0 g/m2 or more, in which in an intensity profile measured by glow discharge optical emission spectrometry, a peak of emission intensity at wavelengths indicating Si is detected within a range from a surface of the Fe-based electroplating layer to more than 0.2 ?m in a thickness direction and not more than a thickness of the Fe-based electroplating layer, and an average value of C concentration in a region ranging from 10 ?m to 20 ?m in the thickness direction from the surface of the Fe-based electroplating layer is 0.10 mass % or less.
    Type: Application
    Filed: November 5, 2021
    Publication date: April 11, 2024
    Applicant: JFE STEEL CORPORATION
    Inventors: Shunsuke YAMAMOTO, Katsutoshi TAKASHIMA, Yusuke OKUMURA, Tomomi KANAZAWA, Katsuya HOSHINO, Takashi KAWANO, Takako YAMASHITA, Hiroshi MATSUDA, Yoichi MAKIMIZU
  • Patent number: 11719745
    Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: August 8, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Publication number: 20230009665
    Abstract: A signal processing circuit includes a signal path for outputting a first signal included in an input signal from a first output terminal to another signal processor; branch paths one of which extends from a top position located at a position on the signal path and the others which extend from associated branch positions that divide the signal path starting from the top position to the first output terminal into segments in each of which a first amount of delay obtained by equally dividing an amount of delay caused by the signal path and that is added to the first signal; a switch connected to each of the branch paths and switches whether to allow a second signal other than the first signal included in the input signal to pass through the connected branch paths; a variable gain amplifier connected to each of the switches and amplifies the second signal.
    Type: Application
    Filed: April 8, 2022
    Publication date: January 12, 2023
    Applicant: FUJITSU LIMITED
    Inventor: Yoichi Kawano
  • Publication number: 20220413039
    Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.
    Type: Application
    Filed: August 31, 2022
    Publication date: December 29, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Patent number: 11506707
    Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Patent number: 11424240
    Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 23, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Patent number: 11387786
    Abstract: An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Fujitsu Limited
    Inventor: Yoichi Kawano
  • Publication number: 20220169515
    Abstract: Provided is a method for manufacturing a high-density artificial graphite electrode without substantially changing a particle size or a proportion of needle coke used, increasing an amount of binder pitch, or performing extrusion molding at a high molding pressure. The method for manufacturing a high-density artificial graphite electrode is kneading binder pitch into needle coke, performing extrusion molding thereof, and then calcining and graphitizing thereof, wherein needle coke obtained by performing coke shape changing treatment for at least some of pulverized needle coke to be used, thereby increasing a ratio of an enveloping perimeter/a perimeter by 1% or more as compared with a value before the changing is used. Here, the enveloping perimeter is a length of a perimeter when apexes of convex portions of the pulverized needle coke are connected to each other via the shortest distance, and the perimeter is a length of a perimeter of a particle.
    Type: Application
    Filed: March 27, 2020
    Publication date: June 2, 2022
    Applicant: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventor: Yoichi Kawano
  • Patent number: 11286165
    Abstract: The present invention provides a method for producing an artificial graphite electrode that enables kneading and subsequent mixing to be carried out without having to increase an amount of binder pitch used even in the case of needle coke having a large pore volume. An artificial graphite electrode is produced by kneading binder pitch with needle coke, and performing extrusion molding and then performing baking and graphitization process on the same, wherein a process for kneading the binder pitch with needle coke includes at least two separate kneading stages, and the amount of binder pitch added and kneading time in these kneading stages satisfy a kneading index as represented by formula (1) below within a range of 0.1 to 0.7.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 29, 2022
    Assignee: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventor: Yoichi Kawano
  • Patent number: 11218117
    Abstract: An amplifier circuit includes: a plurality of amplifiers; a plurality of monitor elements provided for each of the plurality of amplifiers and disposed on a same chip with the corresponding amplifier; and a processor configured to: measure characteristics of each of the plurality of monitor elements; reduce a difference in distortion between a plurality of signals output from the plurality of amplifiers based on the measured characteristics; and compensate for the distortion.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 4, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Masayuki Hosoda, Yoichi Kawano, Alexander Nikolaevich Lozhkin
  • Patent number: 11139254
    Abstract: A semiconductor device includes: a semiconductor substrate; a first metal ring which is provided outside a periphery of a circuit region including a signal pad on one surface side of the semiconductor substrate and is interrupted by one or a plurality of openings; a second metal ring provided outside a periphery of the first metal ring; and a resistance layer that connects ends of the first metal ring interrupted by the one or the plurality of openings to each other, wherein the first metal ring includes a first wall portion and a second wall portion that sandwich the circuit region, and a third wall portion and a fourth wall portion that sandwich the circuit region and are connected to the first wall portion and the second wall portion, and the one or the plurality of openings is arranged in the first wall portion close to the signal pad.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 5, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yoichi Kawano
  • Publication number: 20210281224
    Abstract: An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.
    Type: Application
    Filed: December 22, 2020
    Publication date: September 9, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Yoichi Kawano
  • Patent number: 11069634
    Abstract: An amplifier includes an amplifier circuit configured to include a transistor that amplifies a signal, an insulating film provided over the amplifier circuit, an input pad provided over the insulating film and coupled to the transistor through a wiring in the insulating film, an output pad provided over the insulating film and coupled to the transistor through the wiring in the insulating film, and a metal layer provided over the insulating film to be grounded, and configured to include an opening that extends in a second direction intersecting with a first direction in a plane direction, the signal propagating from the input pad to the output pad in the first direction, and the opening being at a position overlapping the transistor.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Publication number: 20210043586
    Abstract: A semiconductor device includes: a semiconductor substrate; a first metal ring which is provided outside a periphery of a circuit region including a signal pad on one surface side of the semiconductor substrate and is interrupted by one or a plurality of openings; a second metal ring provided outside a periphery of the first metal ring; and a resistance layer that connects ends of the first metal ring interrupted by the one or the plurality of openings to each other, wherein the first metal ring includes a first wall portion and a second wall portion that sandwich the circuit region, and a third wall portion and a fourth wall portion that sandwich the circuit region and are connected to the first wall portion and the second wall portion, and the one or the plurality of openings is arranged in the first wall portion close to the signal pad.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 11, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Yoichi Kawano
  • Publication number: 20210011077
    Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.
    Type: Application
    Filed: June 25, 2020
    Publication date: January 14, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Patent number: 10868573
    Abstract: An antenna integrated amplifier includes a board configured to include an antenna, a radiator that faces the board, a first supporter interposed between the board and the radiator to support the board with respect to the radiator, and configured to include an amplifier to amplify a signal communicated by the antenna, a first bump interposed between the board and the first supporter to be electrically coupled to the antenna and the amplifier, a second supporter interposed between the board and the radiator to support the board with respect to the radiator, and a second bump interposed between the board and the second supporter.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Publication number: 20200161258
    Abstract: An amplifier includes an amplifier circuit configured to include a transistor that amplifies a signal, an insulating film provided over the amplifier circuit, an input pad provided over the insulating film and coupled to the transistor through a wiring in the insulating film, an output pad provided over the insulating film and coupled to the transistor through the wiring in the insulating film, and a metal layer provided over the insulating film to be grounded, and configured to include an opening that extends in a second direction intersecting with a first direction in a plane direction, the signal propagating from the input pad to the output pad in the first direction, and the opening being at a position overlapping the transistor.
    Type: Application
    Filed: October 24, 2019
    Publication date: May 21, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Publication number: 20200144249
    Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.
    Type: Application
    Filed: October 2, 2019
    Publication date: May 7, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Publication number: 20200136568
    Abstract: An amplifier circuit includes: a plurality of amplifiers; a plurality of monitor elements provided for each of the plurality of amplifiers and disposed on a same chip with the corresponding amplifier; and a processor configured to: measure characteristics of each of the plurality of monitor elements; reduce a difference in distortion between a plurality of signals output from the plurality of amplifiers based on the measured characteristics; and compensate for the distortion.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 30, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Masayuki Hosoda, Yoichi Kawano, Alexander Nikolaevich LOZHKIN
  • Publication number: 20200127690
    Abstract: An antenna integrated amplifier includes a board configured to include an antenna, a radiator that faces the board, a first supporter interposed between the board and the radiator to support the board with respect to the radiator, and configured to include an amplifier to amplify a signal communicated by the antenna, a first bump interposed between the board and the first supporter to be electrically coupled to the antenna and the amplifier, a second supporter interposed between the board and the radiator to support the board with respect to the radiator, and a second bump interposed between the board and the second supporter.
    Type: Application
    Filed: September 25, 2019
    Publication date: April 23, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano