Abstract: A base station apparatus performs: determining whether to change an operation of a time-division duplex (TDD) pattern indicating a configuration of uplink communication and downlink communication used when communicating with an user equipment connecting to the base station using TDD; making a notification of information, in a case where the operation is determined to be changed, before changing a first TDD pattern being used for the operation to a second TDD pattern planned to be changed, for determining the second TDD pattern to a relay apparatus that relays communication of the base station apparatus and communicates with second user equipment using TDD; and changing the operation of the TDD pattern to the second TDD pattern after the information for determining the second TDD pattern is notified.

Abstract: There is provided an image pickup element including a non-planar layer having a non-planar light incident surface in a light receiving region, and a microlens of an inorganic material which is provided on a side of the light incident surface of the non-planar layer, and collects incident light.

Abstract: There is provided a communication apparatus functioning as a node that relays a communication between a User Equipment and a base station. The communication apparatus comprises: decision unit configured to decide, in a state in which the User Equipment and the communication apparatus are Radio Resource Control (RRC)-connected and the communication apparatus is connected to a first base station, whether to switch the base station, to which the User Equipment is connected via the communication apparatus, from the first base station to a second base station; and request unit configured to request, in a case where the decision unit decides to switch the base station connected to the User Equipment to the second base station, the User Equipment to release the RRC connection.

Abstract: A communication apparatus that performs communication that uses Transmission Control Protocol (TCP) via one or more network slices determines a respective configuration of the one or more network slices based on a respective state of the communication that uses TCP in the one or more network slices and a respective required quality in the one or more network slices, and makes a request to an apparatus that manages the one or more network slices so as to perform the determined configuration.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Abstract: A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).

Abstract: A semiconductor device includes a first circuit and a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit. A pattern-generator control circuit controls each of the plurality of pattern generators such that the pattern generator starts to operate when a control signal is at a first level and the pattern generator stops operating when the control signal is not at the first level. A pattern compressor compresses a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators. A pattern-compressor control circuit controls the pattern compressor.

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Abstract: A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Abstract: A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.

Abstract: A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST.

Abstract: A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST.