Patents by Inventor Yoichi Matsumura

Yoichi Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10413701
    Abstract: A medical tube in which an intermediate layer composed of a composition containing (a), (b), and (c1) listed below and a lubricant layer composed of a composition containing (a), (b), and (c2) listed below are sequentially laminated on a surface of an insertion member to be inserted into a living body: (a) 1 to 35 weight % of at least one of aromatic diisocyanate, aliphatic diisocyanate, and alicyclic diisocyanate; (b) 1 to 35 weight % of trifunctional or higher functionality polyol; (c1) 30 to 98 weight % of polyalkylene glycol and/or monomethoxypolyalkylene glycol; and (c2) 30 to 98 weight % of polyalkylene glycol (including polyalkylene glycol larger in weight-average molecular weight than polyalkylene glycol in (c1)) and/or monomethoxypolyalkylene glycol (including monomethoxypolyalkylene glycol larger in weight-average molecular weight than monomethoxypolyalkylene glycol in (c1)), (where each of the glycols in (c1) and (c2) is diol).
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 17, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Mariko Matsumoto, Yoichi Matsumura, Hidekazu Miyauchi
  • Patent number: 9318470
    Abstract: In a semiconductor device, a lower chip includes a first group of connection terminals provided on a straight region including a corner region and a region extending from the corner region along one side. An upper chip includes a second group of connection terminals. The upper chip and the lower chip are arranged so that the first group of connection terminals at least partially overlaps with the second group of connection terminals. The first group of connection terminals is at least partially electrically connected to the second group of connection terminals.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 19, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Yoichi Matsumura, Fumihiro Kimura, Wataru Satou, Mitsumi Itou
  • Publication number: 20150340340
    Abstract: In a semiconductor device (1), a lower chip (20) includes a first group of connection terminals (26) provided on a straight region (34) including a corner region (32) and a region extending from the corner region along one side. An upper chip (10) includes a second group of connection terminals (12). The upper chip (10) and the lower chip (20) are arranged so that the first group of connection terminals (26) at least partially overlaps with the second group of connection terminals (12). The first group of connection terminals (26) is at least partially electrically connected to the second group of connection terminals (12).
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Inventors: Yoichi MATSUMURA, Fumihiro KIMURA, Wataru SATOU, Mitsumi ITOU
  • Publication number: 20150018962
    Abstract: A medical tube in which an intermediate layer composed of a composition containing (a), (b), and (c1) listed below and a lubricant layer composed of a composition containing (a), (b), and (c2) listed below are sequentially laminated on a surface of an insertion member to be inserted into a living body: (a) 1 to 35 weight % of at least one of aromatic diisocyanate, aliphatic diisocyanate, and alicyclic diisocyanate; (b) 1 to 35 weight % of trifunctional or higher functionality polyol; (c1) 30 to 98 weight % of polyalkylene glycol and/or monomethoxypolyalkylene glycol; and (c2) 30 to 98 weight % of polyalkylene glycol (including polyalkylene glycol larger in weight-average molecular weight than polyalkylene glycol in (c1)) and/or monomethoxypolyalkylene glycol (including monomethoxypolyalkylene glycol larger in weight-average molecular weight than monomethoxypolyalkylene glycol in (c1)), (where each of the glycols in (c1) and (c2) is diol).
    Type: Application
    Filed: January 25, 2013
    Publication date: January 15, 2015
    Inventors: Mariko Matsumoto, Yoichi Matsumura, Hidekazu Miyauchi
  • Patent number: 8780175
    Abstract: A picture signal processor includes: a frame-rate conversion section performing a frame-rate-increasing conversion, which brings an over-double frame rate, on each of a plurality of time-series picture streams each including a plurality of unit pictures, and providing frame-rate-converted picture streams to a display section which displays pictures through performing time-divisional switching of picture streams from one to another in order; and a shutter control section controlling a shutter eyeglass device to perform an open/close operation in synchronization with a display switching timing between the frame-rate-converted picture streams in the display section.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 15, 2014
    Assignee: Sony Corporation
    Inventors: Shinichiro Miyazaki, Kyoichiro Oda, Minoru Urushihara, Makoto Kondo, Yoichi Matsumura, Hideki Watanabe
  • Patent number: 8647718
    Abstract: A lubricant surface coating having good lubricity and high durability, comprising (A) an urethane polymer layer comprising (a) 40 to 80% by weight of at least one component selected from an aromatic diisocyanate, an aliphatic diisocyanate and an alicyclic diisocyanate and (b) 20 to 60% by weight of a polyol having at least trifunctionality and (B) a hydrophilic polymer layer provided as the outer layer for the urethane polymer layer which comprises a polyalkylene glycol and/or a monomethoxypolyalkylene glycol; and a medical device having the surface coating.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: February 11, 2014
    Assignee: Kaneka Corporation
    Inventors: Yoichi Matsumura, Shuhei Taniguchi
  • Patent number: 8487423
    Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoichi Matsumura, Chie Kabuo, Takako Ohashi, Tadafumi Kadota, Kazuhiko Fujimoto, Hirofumi Miyashita
  • Publication number: 20110285816
    Abstract: A picture signal processor includes: a frame-rate conversion section performing a frame-rate-increasing conversion, which brings an over-double frame rate, on each of a plurality of time-series picture streams each including a plurality of unit pictures, and providing frame-rate-converted picture streams to a display section which displays pictures through performing time-divisional switching of picture streams from one to another in order; and a shutter control section controlling a shutter eyeglass device to perform an open/close operation in synchronization with a display switching timing between the frame-rate-converted picture streams in the display section.
    Type: Application
    Filed: April 7, 2011
    Publication date: November 24, 2011
    Applicant: Sony Corporation
    Inventors: Shinichiro MIYAZAKI, Kyoichiro Oda, Minoru Urushihara, Makoto Kondo, Yoichi Matsumura, Hideki Watanabe
  • Publication number: 20110260333
    Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 27, 2011
    Applicant: Panasonic Corporation
    Inventors: Yoichi MATSUMURA, Chie Kabuo, Takako Ohashi, Tadafumi Kadota, Kazuhiko Fujimoto, Hirofumi Miyashita
  • Patent number: 8028264
    Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Junichi Shimada, Fumihiro Kimura, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino, Takayuki Araki, Yukiji Hashimoto, Takuya Yasui, Hirofumi Taguchi
  • Patent number: 7913221
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto
  • Publication number: 20100041783
    Abstract: It is intended to provide a resin foam which can be preferably used for medical use, and a flexible silicone type resin foam having a water-absorbing property. The resin foam which has a low toxicity and excellent physical properties for medical use such as moisture permeability, skin compatibility and low irritation can be obtained by using a resin which has a siloxane unit and an oxyalkylene unit in its molecular structure and does not contain a unit derived from an isocyanate group. Further, the flexible silicone type resin foam having a water-absorbing property can be obtained by allowing it to have a specific resin composition and a foam structure.
    Type: Application
    Filed: September 11, 2007
    Publication date: February 18, 2010
    Applicant: KANEKA CORPORATION
    Inventors: Masaoki Goto, Yoichi Matsumura, Shuhei Taniguchi, Miaki Shibaya, Kohei Fukaya, Takaoki Saneyasu, Masaki Ichimura
  • Publication number: 20090270291
    Abstract: A lubricant surface coating having good lubricity and high durability, comprising (A) an urethane polymer layer comprising (a) 40 to 80% by weight of at least one component selected from an aromatic diisocyanate, an aliphatic diisocyanate and an alicyclic diisocyanate and (b) 20 to 60% by weight of a polyol having at least trifunctionality and (B) a hydrophilic polymer layer provided as the outer layer for the urethane polymer layer which comprises a polyalkylene glycol and/or a monomethoxypolyalkylene glycol; and a medical device having the surface coating.
    Type: Application
    Filed: March 8, 2006
    Publication date: October 29, 2009
    Applicant: Kaneka Corporation
    Inventors: Yoichi Matsumura, Shuhei Taniguchi
  • Publication number: 20080141202
    Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
    Type: Application
    Filed: January 10, 2008
    Publication date: June 12, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoichi MATSUMURA, Takako OHASHI, Katsuya FUJIMURA, Chihiro ITOH, Hiroki TANIGUCHI
  • Patent number: 7379479
    Abstract: The present invention is an apparatus and method to remove delay fluctuations generated on a plurality of networks. A reception apparatus 22 receives ATM cells transmitted through a network 4-1 and a network 4-2, converting the cells into a transport stream. At that time, the reception apparatus 22 expresses a PCR packet's timing of arrival at the reception apparatus 22 by a count value obtained as a result of counting the number of clock pulses (clock pulses Nr) synchronous with a network clock signal of the network 4-2. The reception apparatus 22 also computes a new PCR value W on the basis of the count value and the phase-difference information used as synchronization information. The reception apparatus 22 then computes a new PCR value X on the basis of an original PCR value E recorded from the beginning on the encoding side and the PCR value W, newly recording the PCR value X.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 27, 2008
    Assignee: Sony Corporation
    Inventors: Yoichi Matsumura, Katsumi Tahara, Hiroaki Seto, Eisaburo Itakura, Hiroshi Meguro
  • Publication number: 20080097641
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto
  • Patent number: 7334210
    Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: February 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoichi Matsumura, Takako Ohashi, Katsuya Fujimura, Chihiro Itoh, Hiroki Taniguchi
  • Publication number: 20070252258
    Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Junichi Shimada, Fumihiro Kimura, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino, Takayuki Araki, Yukiji Hashimoto, Takuya Yasui, Hirofumi Taguchi
  • Patent number: 7195816
    Abstract: To provide an acrylic film, composed of a resin composition (C) that includes an acrylic graft copolymer (A) containing an acrylic ester rubber-like polymer and a methacrylic polymer (B) containing 80% by weight or more of methyl methacrylate, wherein (1) the content of the acrylic ester rubber-like polymer in the resin composition (C) is 5% by weight or more and 30% by weight or less, (2) the average particle size of the acrylic ester rubber-like polymer is 500 to 2000 ?, (3) the relationship between the average particle size d (?) of the acrylic ester rubber-like polymer and the amount w (% by weight) of crosslinking agent used in the acrylic ester rubber-like polymer satisfies the following equation: 0.002d?w?0.005d, (4) the graft ratio of the acrylic graft copolymer (A) is 30% or more and 200% or less, and (5) the reduced viscosity of methyl ethyl ketone soluble matter in the resin composition (C) is 0.2 to 0.8 dl/g.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 27, 2007
    Assignee: Kaneka Corporation
    Inventors: Norito Doi, Takao Shibata, Yoichi Matsumura, Shigemi Matsumoto
  • Publication number: 20060253823
    Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 9, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoichi Matsumura, Takako Ohashi, Katsuya Fujimura, Chihiro Itoh, Hiroki Taniguchi