Patents by Inventor Yoichi Moriya

Yoichi Moriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230274851
    Abstract: A surface electrode having a first surface and a plurality of electrode elements disposed on the first surface and spaced from each other in a manner so as to be configured to contact a measured surface of an object to be measured; a stretchable wire electrically connecting the plurality of electrode elements; and a stretchable insulator covering a side of the stretchable wire adjacent to the electrode elements.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Tomoki OUCHI, Yoichi MORIYA, Kahori TAKATSUKI, Koji TANAKA
  • Publication number: 20230270365
    Abstract: An elastically deformable electrode that includes a plurality of electrode elements spaced from each other, and a liquid wire which is a liquid conductor configured to electrically connect the plurality of electrode elements. The electrode may also include a solid wire sealing the liquid wire, and an insulator between the solid wire and the plurality of electrode elements.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Tomoki OUCHI, Yoichi Moriya, Kahori Takatsuki, Koji Tanaka, Katsuhisa Higashiyama
  • Patent number: 11114355
    Abstract: A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Hayakawa, Yasutaka Sugimoto, Tomoki Kato, Yoichi Moriya
  • Patent number: 11107741
    Abstract: A composite ceramic multilayer substrate includes a glass ceramic insulating layer including a wiring layer and a highly thermally conductive ceramic insulating layer made of a ceramic material having a higher thermal conductivity than the glass ceramic insulating layer. The glass ceramic insulating layer is provided on at least one main surface of the highly thermally conductive ceramic insulating layer directly and/or with a wiring layer interposed therebetween. When viewed in a direction perpendicular or substantially perpendicular to a main surface of the composite ceramic multilayer substrate, the composite ceramic multilayer substrate includes at least one heat generating element-mounting portion surrounded by the glass ceramic insulating layer and at which a heat generating element-mounting wiring line provide on the main surface of the highly thermally conductive ceramic insulating layer is exposed.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomoki Kato, Yasutaka Sugimoto, Yoichi Moriya, Takahiro Hayakawa
  • Publication number: 20190371702
    Abstract: A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Takahiro HAYAKAWA, Yasutaka SUGIMOTO, Tomoki KATO, Yoichi MORIYA
  • Publication number: 20190371689
    Abstract: A composite ceramic multilayer substrate includes a glass ceramic insulating layer including a wiring layer and a highly thermally conductive ceramic insulating layer made of a ceramic material having a higher thermal conductivity than the glass ceramic insulating layer. The glass ceramic insulating layer is provided on one main surface of the highly thermally conductive ceramic insulating layer or both main surfaces of the highly thermally conductive ceramic insulating layer directly and/or with a wiring layer interposed therebetween. When viewed in a direction perpendicular or substantially perpendicular to a main surface of the composite ceramic multilayer substrate, the composite ceramic multilayer substrate includes at least one heat generating element-mounting portion surrounded by the glass ceramic insulating layer and at which a heat generating element-mounting wiring line provide on the main surface of the highly thermally conductive ceramic insulating layer is exposed.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Tomoki KATO, Yasutaka SUGIMOTO, Yoichi MORIYA, Takahiro HAYAKAWA
  • Publication number: 20150173185
    Abstract: A circuit board structure and a manufacturing method for a circuit board that ensures an electrical connection between a metal foil and a projection without using a conductive adhesive and is less likely to cause a decrease in the reliability of the connection due to the interlayer separation or the like is provided. A circuit board includes an insulating layer, a lower main surface wiring pattern and an upper main surface wiring pattern disposed on either side of the insulating layer, and an interlayer connection conductor passing through the insulating layer in a thickness direction and electrically connecting to the lower main surface wiring pattern and the upper main surface wiring pattern. The interlayer connection conductor is formed integrally with the lower main surface wiring pattern, and is bonded to the upper main surface wiring pattern via an intermetallic compound.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 18, 2015
    Inventors: Satoshi Ito, Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yuki Yamamoto
  • Patent number: 9030005
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Patent number: 8980028
    Abstract: In a metal base substrate with a low-temperature sintering ceramic layer located on a copper substrate, bonding reliability is increased between the copper substrate and the low-temperature sintering ceramic layer. A raw laminated body is prepared by stacking, on a surface of a copper substrate, a low-temperature sintering ceramic green layer including a low-temperature sintering ceramic material containing about 10 mol % to about 40 mol % of barium in terms of BaO and about 40 mol % to about 80 mol % of silicon in terms of SiO2, and this raw laminated body is subjected to firing at a temperature at which the low-temperature sintering ceramic green layer is sintered. In the thus obtained metal base substrate, a glass layer composed of Cu—Ba—Si based glass with a thickness of about 1 ?m to about 5 ?m is formed between the metal substrate and the low-temperature sintering ceramic layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tsuyoshi Katsube, Yuki Takemori, Tetsuo Kanamori, Yasutaka Sugimoto, Takahiro Takada
  • Patent number: 8975743
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Publication number: 20140118977
    Abstract: A wiring board includes an insulating layer, and an upper wiring pattern and a lower wiring pattern arranged with the insulating layer interposed therebetween. A truncated cone-shaped projection is integral with the lower wiring pattern so as to project at the upper wiring pattern side, and a truncated cone-shaped projection is integral with the upper wiring pattern so as to project at the lower wiring pattern side. Bonding end portions of the projections are bonded to each other to form an inter-layer connection conductor. The inter-layer connection conductor conducts the upper wiring pattern and the lower wiring pattern.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi ITO, Yoichi MORIYA, Tetsuo KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Patent number: 8652982
    Abstract: Provided is a mono- or multilayer ceramic substrate which exhibits a high flexural strength. The substrate contains a sintered ceramic which includes respective crystal phases of quartz, alumina, fresnoite, sanbornite, and celsian, in which the relationship between the diffraction peak intensity A in the (201) plane of the fresnoite and the diffraction peak intensity B in the (110) plane of the quartz, measured by a powder X-ray diffractometry in the range of the diffraction peak angle 2?=10 to 40°, is A/B?2.5. The fresnoite crystal phase preferably has an average crystal grain size of 5 ?m or less. In firing to obtain this ceramic sintered body, the maximum temperature falls within the range of 980 to 1000° C.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Machiko Motoya, Takahiro Sumi, Tsuyoshi Katsube, Yoichi Moriya
  • Publication number: 20140022750
    Abstract: A circuit board includes an insulating layer with a surface on which a semiconductor element is to be mounted and wiring portions that are located on the insulating layer. The wiring portions includes upper wiring portions, lower wiring portions, and interlayer wiring portions. The upper wiring portions, the lower wiring portions, and the interlayer wiring portions are integrally defined by a single copper sheet. With this configuration, a circuit board capable of withstanding a large current and a method of manufacturing the circuit board are provided.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 23, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi MORIYA, Satoshi ITO, Tetsuo KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Publication number: 20140009899
    Abstract: A wiring substrate includes an insulating layer, an upper wiring pattern, and a lower wiring pattern, the wiring patterns sandwiching the insulating layer. The lower wiring pattern includes an interlayer connecting conductor integral therewith and projecting toward the upper wiring pattern for electrical connection to the upper wiring pattern. The interlayer connecting conductor is joined to the upper wiring pattern so as to penetrate into the upper wiring pattern beyond a joining interface between the insulating layer and the upper wiring pattern. Thus, the wiring substrate adaptable for a large current is provided without causing degradation of reliability in connection, which may occur by cracking, disconnection, interlayer peeling-off, etc.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 9, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi ITO, Yoichi MORIYA, Tetso KANAMORI, Yukihiro YAGI, Yuki YAMAMOTO
  • Publication number: 20130266782
    Abstract: In a metal base substrate with a low-temperature sintering ceramic layer provided on a metal substrate, while making it possible to make the metal substrate from copper, the low-temperature sintering ceramic layer is less likely to crack or peel at the interface with the metal substrate, and the anti-peeling strength of a surface conductor is improved. In the metal base substrate, the thermal expansion coefficient of the metal substrate is greater than the thermal expansion coefficient of the low-temperature sintering ceramic layer, the average difference in thermal expansion coefficients of the metal substrate and the low-temperature sintering ceramic layer at approximately 25° C. to 400° C. is about 4 ppm/° C. to about 9 ppm/° C., and the low-temperature sintering ceramic layer has a Young's modulus less than about 120 GPa, and a flexural strength of about 200 MPa or more.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 10, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoichi MORIYA, Tsuyoshi KATSUBE, Yuki TAKEMORI, Yasutaka SUGIMOTO, Takahiro TAKADA
  • Publication number: 20130264723
    Abstract: In a metal base substrate with a low-temperature sintering ceramic layer located on a copper substrate, bonding reliability is increased between the copper substrate and the low-temperature sintering ceramic layer. A raw laminated body is prepared by stacking, on a surface of a copper substrate, a low-temperature sintering ceramic green layer including a low-temperature sintering ceramic material containing about 10 mol % to about 40 mol % of barium in terms of BaO and about 40 mol % to about 80 mol % of silicon in terms of SiO2, and this raw laminated body is subjected to firing at a temperature at which the low-temperature sintering ceramic green layer is sintered. In the thus obtained metal base substrate, a glass layer composed of Cu—Ba—Si based glass with a thickness of about 1 ?m to about 5 ?m is formed between the metal substrate and the low-temperature sintering ceramic layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 10, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoichi MORIYA, Tsuyoshi KATSUBE, Yuki TAKEMORI, Tetsuo KANAMORI, Yasutaka SUGIMOTO, Takahiro TAKADA
  • Patent number: 8361918
    Abstract: To provide a ceramic composition not only having little compositional variation after burning, but a high flexural strength of the sintered body, and a high Q value in a microwave band, a ceramic composition used for forming a ceramic layer of a multi-layer ceramic substrate contains 47.0 to 67.0 wt. % of SiO2, 21.0 to 41.0 wt. % of BaO, and 10.0 to 18.0 wt. % of Al2O3, and contains as a first additive, 1.0 to 5.0 parts by weight of CeO2, relative to a total of 100 parts of SiO2, BaO and Al2O3, and as a second additive, 2.5 to 5.5 parts by weight of MnO, relative to a total of 100 parts by weight of SiO2, BaO, Al2O3 and CeO2, and is substantially free of Cr. As a third additive, at least one of Zr, Ti, Zn, Nb, Mg and Fe, and as a fourth additive, a Co component and/or a V component, may be contained.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: January 29, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Machiko Motoya, Tsutomu Tatekawa, Jun Urakawa, Tsuyoshi Katsube, Yoichi Moriya
  • Publication number: 20120329633
    Abstract: Provided is a mono- or multilayer ceramic substrate which exhibits a high flexural strength. The substrate contains a sintered ceramic which includes respective crystal phases of quartz, alumina, fresnoite, sanbornite, and celsian, in which the relationship between the diffraction peak intensity A in the (201) plane of the fresnoite and the diffraction peak intensity B in the (110) plane of the quartz, measured by a powder X-ray diffractometry in the range of the diffraction peak angle 2?=10 to 40°, is A/B?2.5. The fresnoite crystal phase preferably has an average crystal grain size of 5 ?m or less. In firing to obtain this ceramic sintered body, the maximum temperature falls within the range of 980 to 1000° C.
    Type: Application
    Filed: August 6, 2012
    Publication date: December 27, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Machiko Motoya, Takahiro Sumi, Tsuyoshi Katsube, Yoichi Moriya
  • Patent number: 7824642
    Abstract: A forsterite powder with superior characteristics which can be sintered at a relatively low temperature can be economically produced, when a magnesium source, a silicon source, and copper particles are mixed to prepare a mixed powder containing 300 to 2,000 ppm by weight of the copper particles, and the mixed powder is fired. The magnesium source used is preferably Mg(OH)2, and the silicon source used is preferably SiO2. A polycrystalline forsterite powder is preferably produced. The magnesium source, the silicon source, and the copper particles can be mixed in the presence of a solvent to prepare the mixed powder. The forsterite powder preferably contains 300 to 2,000 ppm by weight of copper, has a particle size of 0.20 to 0.40 ?m and has a crystal size of 0.034 to 0.040 ?m.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: November 2, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Naoya Mori
  • Publication number: 20100170705
    Abstract: A forsterite powder with superior characteristics which can be sintered at a relatively low temperature can be economically produced, when a magnesium source, a silicon source, and copper particles are mixed to prepare a mixed powder containing 300 to 2,000 ppm by weight of the copper particles, and the mixed powder is fired. The magnesium source used is preferably Mg(OH)2, and the silicon source used is preferably SiO2. A polycrystalline forsterite powder is preferably produced. The magnesium source, the silicon source, and the copper particles can be mixed in the presence of a solvent to prepare the mixed powder. The forsterite powder preferably contains 300 to 2,000 ppm by weight of copper, has a particle size of 0.20 to 0.40 ?m and has a crystal size of 0.034 to 0.040 ?m.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 8, 2010
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoichi MORIYA, Naoya Mori