Patents by Inventor Yoichi Negoro
Yoichi Negoro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11493671Abstract: There is provided a stacked lens structure including a first lens substrate having a first through-hole and a second lens substrate having a second-through hole. The first lens substrate may be directly bonded to the second lens substrate. The stacked lens structure may include lens resin portions, where each lens resin portion includes a lens portion configured to refract light, and a support portion configured to support the lens portion at a corresponding lens substrate, the support portion including a first portion at a side of the lens substrate, a second portion, and a third portion, where the first portion is between the lens substrate and the second portion in a cross-section view, and the third portion is between the second portion and the lens portion in the cross-section view.Type: GrantFiled: January 16, 2018Date of Patent: November 8, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Mitsunari Hoshi, Yoichi Negoro
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Publication number: 20200124774Abstract: There is provided a stacked lens structure including a first lens substrate having a first through-hole and a second lens substrate having a second-through hole. The first lens substrate may be directly bonded to the second lens substrate. The stacked lens structure may include lens resin portions, where each lens resin portion includes a lens portion configured to refract light, and a support portion configured to support the lens portion at a corresponding lens substrate, the support portion including a first portion at a side of the lens substrate, a second portion, and a third portion, where the first portion is between the lens substrate and the second portion in a cross-section view, and the third portion is between the second portion and the lens portion in the cross-section view.Type: ApplicationFiled: January 16, 2018Publication date: April 23, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Mitsunari HOSHI, Yoichi NEGORO
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Patent number: 9488886Abstract: A display unit includes: a base; a display layer having a first end surface; and a wiring layer disposed between the base and the display layer, the wiring layer being provided in a region differing from a position corresponding to the first end surface.Type: GrantFiled: March 21, 2014Date of Patent: November 8, 2016Assignee: Sony CorporationInventors: Hirofumi Nakamura, Shota Nishi, Yoichi Negoro, Hidehiko Takanashi
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Publication number: 20140300850Abstract: A display unit includes: a base; a display layer having a first end surface; and a wiring layer disposed between the base and the display layer, the wiring layer being provided in a region differing from a position corresponding to the first end surface.Type: ApplicationFiled: March 21, 2014Publication date: October 9, 2014Applicant: Sony CorporationInventors: Hirofumi Nakamura, Shota Nishi, Yoichi Negoro, Hidehiko Takanashi
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Patent number: 7507642Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: GrantFiled: May 11, 2007Date of Patent: March 24, 2009Assignee: Sony CorporationInventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
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Publication number: 20070287268Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: ApplicationFiled: May 11, 2007Publication date: December 13, 2007Applicant: SONY CORPORATIONInventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
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Patent number: 7303979Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: GrantFiled: April 6, 2004Date of Patent: December 4, 2007Assignee: Sony CorporationInventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
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Patent number: 7157344Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: GrantFiled: December 20, 2001Date of Patent: January 2, 2007Assignee: Sony CorporationInventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
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Publication number: 20040191960Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: ApplicationFiled: April 6, 2004Publication date: September 30, 2004Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
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Publication number: 20030134491Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.Type: ApplicationFiled: December 2, 2002Publication date: July 17, 2003Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsuhiro Hirata, Takashi Noguchi
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Publication number: 20020151115Abstract: A process for producing a thin film (particularly semiconductor thin film) which includes irradiating a raw thin film containing a volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the raw thin film. The process effectively reduces the content of volatile gas such as hydrogen in thin film as in the case where degassing is performed by using an electric furnace. The degassed thin film can be recrystallized in a short time without breaking by irradiation with an excimer laser beam. Alternatively, the process consists of irradiating a thin film containing 2 atom % or more volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the thin film and simultaneously crystallizing the thin film. This procedure brings about uniform nucleation, gives rise to uniform crystal grains, and prevents variation in characteristic properties.Type: ApplicationFiled: December 20, 2001Publication date: October 17, 2002Applicant: Sony CorporationInventors: Hideharu Nakajima, Yoichi Negoro, Setsuo Usui
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Publication number: 20020072252Abstract: A process for producing a thin film (particularly semiconductor thin film) which includes irradiating a raw thin film containing a volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the raw thin film. The process effectively reduces the content of volatile gas such as hydrogen in thin film as in the case where degassing is performed by using an electric furnace. The degassed thin film can be recrystallized in a short time without breaking by irradiation with an excimer laser beam.Type: ApplicationFiled: September 5, 2001Publication date: June 13, 2002Inventors: Hideharu Nakajima, Yoichi Negoro, Setsuo Usui
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Patent number: 5828526Abstract: A magnetoresistance effect element is provided with a magnetoresistance effect film (MR film) formed of alternative laminations of magnetic layers (for example, soft magnetic layers such as Fe--Ni--Co alloy layers) which are coupled anti-ferromagnetically with each other between adjacent magnetic layers and non-magnetic layers (for example, non-magnetic layers such as Cu layers) and provided with a bias soft magnetic layer (for example, SAL layer) for application of a bias magnetic filed to the magnetoresistance effect film, where the anisotropic magnetic field (Hk) in the plane of the bias medium layer is 5 Oe.ltoreq.Hk.ltoreq.15 Oe.Type: GrantFiled: August 1, 1996Date of Patent: October 27, 1998Assignee: Sony CorporationInventors: Kiyoshi Kagawa, Yoichi Negoro, Akihiko Okabe, Hiroshi Kano