Patents by Inventor Yoichi Negoro

Yoichi Negoro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11493671
    Abstract: There is provided a stacked lens structure including a first lens substrate having a first through-hole and a second lens substrate having a second-through hole. The first lens substrate may be directly bonded to the second lens substrate. The stacked lens structure may include lens resin portions, where each lens resin portion includes a lens portion configured to refract light, and a support portion configured to support the lens portion at a corresponding lens substrate, the support portion including a first portion at a side of the lens substrate, a second portion, and a third portion, where the first portion is between the lens substrate and the second portion in a cross-section view, and the third portion is between the second portion and the lens portion in the cross-section view.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 8, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Mitsunari Hoshi, Yoichi Negoro
  • Publication number: 20200124774
    Abstract: There is provided a stacked lens structure including a first lens substrate having a first through-hole and a second lens substrate having a second-through hole. The first lens substrate may be directly bonded to the second lens substrate. The stacked lens structure may include lens resin portions, where each lens resin portion includes a lens portion configured to refract light, and a support portion configured to support the lens portion at a corresponding lens substrate, the support portion including a first portion at a side of the lens substrate, a second portion, and a third portion, where the first portion is between the lens substrate and the second portion in a cross-section view, and the third portion is between the second portion and the lens portion in the cross-section view.
    Type: Application
    Filed: January 16, 2018
    Publication date: April 23, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Mitsunari HOSHI, Yoichi NEGORO
  • Patent number: 9488886
    Abstract: A display unit includes: a base; a display layer having a first end surface; and a wiring layer disposed between the base and the display layer, the wiring layer being provided in a region differing from a position corresponding to the first end surface.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 8, 2016
    Assignee: Sony Corporation
    Inventors: Hirofumi Nakamura, Shota Nishi, Yoichi Negoro, Hidehiko Takanashi
  • Publication number: 20140300850
    Abstract: A display unit includes: a base; a display layer having a first end surface; and a wiring layer disposed between the base and the display layer, the wiring layer being provided in a region differing from a position corresponding to the first end surface.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 9, 2014
    Applicant: Sony Corporation
    Inventors: Hirofumi Nakamura, Shota Nishi, Yoichi Negoro, Hidehiko Takanashi
  • Patent number: 7507642
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: March 24, 2009
    Assignee: Sony Corporation
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
  • Publication number: 20070287268
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Application
    Filed: May 11, 2007
    Publication date: December 13, 2007
    Applicant: SONY CORPORATION
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
  • Patent number: 7303979
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: December 4, 2007
    Assignee: Sony Corporation
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
  • Patent number: 7157344
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: January 2, 2007
    Assignee: Sony Corporation
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
  • Publication number: 20040191960
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Application
    Filed: April 6, 2004
    Publication date: September 30, 2004
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsushiro Hirata, Takashi Noguchi
  • Publication number: 20030134491
    Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.
    Type: Application
    Filed: December 2, 2002
    Publication date: July 17, 2003
    Inventors: Hideo Yamagata, Takeyoshi Koumoto, Kenji Atsuumi, Yoichi Negoro, Tatsuhiro Hirata, Takashi Noguchi
  • Publication number: 20020151115
    Abstract: A process for producing a thin film (particularly semiconductor thin film) which includes irradiating a raw thin film containing a volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the raw thin film. The process effectively reduces the content of volatile gas such as hydrogen in thin film as in the case where degassing is performed by using an electric furnace. The degassed thin film can be recrystallized in a short time without breaking by irradiation with an excimer laser beam. Alternatively, the process consists of irradiating a thin film containing 2 atom % or more volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the thin film and simultaneously crystallizing the thin film. This procedure brings about uniform nucleation, gives rise to uniform crystal grains, and prevents variation in characteristic properties.
    Type: Application
    Filed: December 20, 2001
    Publication date: October 17, 2002
    Applicant: Sony Corporation
    Inventors: Hideharu Nakajima, Yoichi Negoro, Setsuo Usui
  • Publication number: 20020072252
    Abstract: A process for producing a thin film (particularly semiconductor thin film) which includes irradiating a raw thin film containing a volatile gas with an excimer laser beam having a pulse width of 60 ns or more, thereby removing the volatile gas from the raw thin film. The process effectively reduces the content of volatile gas such as hydrogen in thin film as in the case where degassing is performed by using an electric furnace. The degassed thin film can be recrystallized in a short time without breaking by irradiation with an excimer laser beam.
    Type: Application
    Filed: September 5, 2001
    Publication date: June 13, 2002
    Inventors: Hideharu Nakajima, Yoichi Negoro, Setsuo Usui
  • Patent number: 5828526
    Abstract: A magnetoresistance effect element is provided with a magnetoresistance effect film (MR film) formed of alternative laminations of magnetic layers (for example, soft magnetic layers such as Fe--Ni--Co alloy layers) which are coupled anti-ferromagnetically with each other between adjacent magnetic layers and non-magnetic layers (for example, non-magnetic layers such as Cu layers) and provided with a bias soft magnetic layer (for example, SAL layer) for application of a bias magnetic filed to the magnetoresistance effect film, where the anisotropic magnetic field (Hk) in the plane of the bias medium layer is 5 Oe.ltoreq.Hk.ltoreq.15 Oe.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventors: Kiyoshi Kagawa, Yoichi Negoro, Akihiko Okabe, Hiroshi Kano