Patents by Inventor Yoichi Nishihara

Yoichi Nishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145352
    Abstract: A semiconductor device includes a laminate including a semiconductor element, an insulating substrate on a first surface of the semiconductor element, an interconnect on the insulating substrate, and an interconnect member on a second surface of the semiconductor element. The interconnect is electrically connected to a first electrode in the first surface of the semiconductor element through a through hole in the insulating substrate. The interconnect member is electrically connected to a second electrode in the second surface of the semiconductor element. The semiconductor device further includes first and second elastic terminals holding the laminate therebetween. The first terminal includes a bulge that engages with a depression in the interconnect. The second terminal contacts the interconnect member. The semiconductor device further includes a fixing member fixing the first terminal and the second terminal while electrically isolating the first terminal and the second terminal from each other.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventor: Yoichi NISHIHARA
  • Publication number: 20230411274
    Abstract: A semiconductor device includes a lower substrate, a first wiring pattern disposed on the lower substrate with a current input terminal, a semiconductor element mounted on the lower substrate with a first electrode electrically connected to the first wiring pattern and a second electrode opposed to the first wiring pattern, an upper substrate disposed on the second electrode, via wirings extending through the upper substrate and connected to the second electrode, a second wiring pattern disposed on the upper substrate and electrically connected to the second electrode via the via wirings, and a current output terminal. The second wiring pattern is electrically connected to the current output terminal and extends from the second electrode toward the current output terminal in plan view. Among the via wirings, first via wirings closest to the current output terminal are larger than second via wirings adjacent to the first via wirings in plan view.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 21, 2023
    Inventor: Yoichi NISHIHARA
  • Patent number: 11742272
    Abstract: A semiconductor device includes a film substrate, an adhesive on a first surface of the film substrate, an electronic component on the adhesive, a wiring layer on a second surface of the film substrate opposite from the first surface, and a reinforcement member in an area around the electronic component on the adhesive. The wiring layer is connected to the electronic component through a via hole piercing through the film substrate and the adhesive. The reinforcement member has a thickness smaller than the thickness of the electronic component.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: August 29, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoichi Nishihara
  • Patent number: 11735560
    Abstract: An electronic-component-embedded substrate includes a base having flexibility and cavities formed therethrough, electronic components disposed in the cavities, respectively, and interconnects disposed on the base and connected to the electronic components, wherein the interconnects include a metal foil having openings that abut the electronic components, and include a plating layer disposed on the metal foil and connected to the electronic components through the openings.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: August 22, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoichi Nishihara
  • Publication number: 20220208668
    Abstract: A semiconductor device includes a film substrate, an adhesive on a first surface of the film substrate, an electronic component on the adhesive, a wiring layer on a second surface of the film substrate opposite from the first surface, and a reinforcement member in an area around the electronic component on the adhesive. The wiring layer is connected to the electronic component through a via hole piercing through the film substrate and the adhesive. The reinforcement member has a thickness smaller than the thickness of the electronic component.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 30, 2022
    Inventor: Yoichi NISHIHARA
  • Publication number: 20210375818
    Abstract: An electronic-component-embedded substrate includes a base having flexibility and cavities formed therethrough, electronic components disposed in the cavities, respectively, and interconnects disposed on the base and connected to the electronic components, wherein the interconnects include a metal foil having openings that abut the electronic components, and include a plating layer disposed on the metal foil and connected to the electronic components through the openings.
    Type: Application
    Filed: May 19, 2021
    Publication date: December 2, 2021
    Inventor: Yoichi NISHIHARA
  • Patent number: 10297540
    Abstract: A wiring substrate includes a first wiring layer, an insulation layer arranged on the first wiring layer and formed of a photosensitive resin, a via hole formed in the insulation layer and reaching the first wiring layer, and a second wiring layer formed in the via hole and on the insulation layer and connected to the first wiring layer. A surface of the first wiring layer in the via hole is formed as a roughened surface.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 21, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES, CO., LTD.
    Inventor: Yoichi Nishihara
  • Publication number: 20180337117
    Abstract: A wiring substrate includes a first wiring layer, an insulation layer arranged on the first wiring layer and formed of a photosensitive resin, a via hole formed in the insulation layer and reaching the first wiring layer, and a second wiring layer formed in the via hole and on the insulation layer and connected to the first wiring layer. A surface of the first wiring layer in the via hole is formed as a roughened surface.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 22, 2018
    Inventor: Yoichi Nishihara