Abstract: A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a first processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed.

Abstract: There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inner surface of the first hole, a filler body, which is formed with a thickness to fill the first hole on the first conductive film, forms a first conduct plug together with the conductive film, and is formed of an insulating material with an upper surface being amorphous, and a capacitor, which is formed on the first contact plug and is provided with a lower electrode electrically connected to the conductive film, a capacitor dielectric film formed of a ferroelectric material, and an upper electrode.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A plasma etching apparatus for etching semiconductor wafers. The plasma etching apparatus has a reaction tube made of a dielectric material and a high frequency antenna located around the reaction tube for generating a plasma inside the reaction tube. The high frequency antenna has a sloped segment that produces a relatively large capacitive coupling with the reaction tube. The high frequency antenna is moved by a driver around the reaction tube in a horizontal plane.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.

Abstract: In a conventional semiconductor device provided with a conventional stacked type ferroelectric capacitor, there has been caused a problem of capacitor degradation by leakage between an upper electrode and a lower electrode via an etching reside, when the efficiency of utilization of a surface area is increased by decreasing the interval between the capacitors in the in-plane direction of the substrate, as a result of the one-step annealing of the laminated from of lower electrode film/ferroelectric film/upper electrode film. The present invention prevents leakage caused by short circuit between the lower electrode and the upper electrode, by forming plural lower electrodes, forming a ferroelectric film so as to cover the surface and sidewall surface of the lower electrodes and forming an upper electrode on the ferroelectric film so as to oppose with the lower electrodes.

Abstract: An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al2O3 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.

Abstract: There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inner surface of the first hole, a filler body, which is formed with a thickness to fill the first hole on the first conductive film, forms a first conduct plug together with the conductive film, and is formed of an insulating material with an upper surface being amorphous, and a capacitor, which is formed on the first contact plug and is provided with a lower electrode electrically connected to the conductive film, a capacitor dielectric film formed of a ferroelectric material, and an upper electrode.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a fist processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed.

Abstract: A method for fabricating a ferroelectric memory having memory cells arranged in arrays, wherein an Al2O3 film (2), a Pt film (3), a PZT film (4) and IrO2 film (5) are formed on an interlayer insulation film. At the time of forming a top electrode, the IrO2 film (5) is patterned using a resist mask having a part extending in the row direction, and then patterned using a resist mask having a part extending in the column direction. Consequently, a top electrode of the IrO2 film (5) having a rectangular plan view is formed at the intersection of these resist masks.

Abstract: There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.

Abstract: There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.

Abstract: There are provided steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film, that constitute a capacitor, on an insulating film, forming an upper electrode of the capacitor by etching the second conductive film while using a first resist pattern as a mask, removing the first resist pattern, forming second resist patterns, that have a width equal to or smaller than a pattern width of the upper electrode of the capacitor, on the upper electrode of the capacitor, and etching at least a part of the dielectric film and the first conductive film by using the second resist patterns as a mask, while exposing an upper surface of the upper electrode of the capacitor close to side portions by retreating side portions of the second resist patterns.

Abstract: A plasma etching apparatus for etching semiconductor wafers. The plasma etching apparatus has a reaction tube made of a dielectric material and a high frequency antenna located around the reaction tube for generating a plasma inside the reaction tube. The high frequency antenna has a sloped segment that produces a relatively large capacitive coupling with the reaction tube. The high frequency antenna is moved by a driver around the reaction tube in a horizontal plane.

Abstract: A plasma etching apparatus for etching semiconductor wafers. The plasma etching apparatus has a reaction tube made of a dielectric material and a high frequency antenna located around the reaction tube for generating a plasma inside the reaction tube. The high frequency antenna has a sloped segment that produces a relatively large capacitive coupling with the reaction tube. The high frequency antenna is moved by a driver around the reaction tube in a horizontal plane.

Abstract: A method for fabricating a ferroelectric memory having memory cells arranged in arrays, wherein an Al2O3 film (2), a Pt film (3), a PZT film (4) and IrO2 film (5) are formed on an interlayer insulation film. At the time of forming a top electrode, the IrO2 film (5) is patterned using a resist mask having a part extending in the row direction, and then patterned using a resist mask having a part extending in the column direction. Consequently, a top electrode of the IrO2 film (5) having a rectangular plan view is formed at the intersection of these resist masks.

Abstract: An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al203 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.