Patents by Inventor Yoichi Okumura

Yoichi Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117517
    Abstract: Disclosed is an Fe-based electroplated steel sheet including: a Si-containing cold-rolled steel sheet containing Si in an amount of 0.1 mass % or more and 3.0 mass % or less; and an Fe-based electroplating layer formed on at least one surface of the Si-containing cold-rolled steel sheet with a coating weight per surface of 5.0 g/m2 or more, in which in an intensity profile measured by glow discharge optical emission spectrometry, a peak of emission intensity at wavelengths indicating Si is detected within a range from a surface of the Fe-based electroplating layer to more than 0.2 ?m in a thickness direction and not more than a thickness of the Fe-based electroplating layer, and an average value of C concentration in a region ranging from 10 ?m to 20 ?m in the thickness direction from the surface of the Fe-based electroplating layer is 0.10 mass % or less.
    Type: Application
    Filed: November 5, 2021
    Publication date: April 11, 2024
    Applicant: JFE STEEL CORPORATION
    Inventors: Shunsuke YAMAMOTO, Katsutoshi TAKASHIMA, Yusuke OKUMURA, Tomomi KANAZAWA, Katsuya HOSHINO, Takashi KAWANO, Takako YAMASHITA, Hiroshi MATSUDA, Yoichi MAKIMIZU
  • Publication number: 20240109484
    Abstract: A lighting device includes a light source portion, a light guide that includes a light guide body with an elongated shape, guides light incident from the light source portion in a longitudinal direction of the elongated shape, and emits the light in an emission direction substantially orthogonal to the longitudinal direction, and a bezel that is provided along the light guide and includes an elongated-shaped opening through which the light emitted from the light guide passes and is emitted to the outside. The bezel includes at least one bridge portion that is formed along a lateral direction of the opening so as to partially bridge opposed walls of the opening in the lateral direction.
    Type: Application
    Filed: August 15, 2023
    Publication date: April 4, 2024
    Inventors: Toshiaki MORI, Yoichi MATSUOKA, Takao OKUMURA, Koichiro ENDO
  • Publication number: 20230294046
    Abstract: A membrane treatment apparatus (1) comprising: a plurality of flat membrane elements (2) which are immersed in a liquid to be treated, disposed side by side in the first direction so that membrane surfaces face each other; a supporting member (8) for holding the flat membrane element (2) provided at an end part of the flat membrane element on a first side in the second direction; and an aeration means (10) provided below the flat membrane element (2); wherein a lower edge of the flat membrane element (2) is formed to extend upward from the first side to a second side in the second direction, or to extend upward and horizontally from the first side to the second side in the second direction.
    Type: Application
    Filed: October 11, 2021
    Publication date: September 21, 2023
    Inventors: Yasuhiro OKAWA, Yoichi OKUMURA, Hiroki TOMITA, Jun MAEDA, Hiroyuki KOBAYASHI
  • Patent number: 11675550
    Abstract: An information processing apparatus includes: a display controller; a letter-size setting section that sets a letter size of a letter string over a plurality of lines which has been entered through an edit screen; and a print controller that prints the letter string in the letter size set by the letter-size setting section. The letter-size setting section can differently set letter sizes of the letter string. When a line feed operation is performed at a head or end of an n-th line through the edit screen, a letter size of the n-th line preset in accordance with a user's designation, the letter-size setting section sets a letter size of one of the n-th line and an (n+1)-th line after the line feed operation so that a length of letter string over the plurality of lines is equal to or shorter than a length of the printable area.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 13, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yoichi Okumura
  • Publication number: 20220374177
    Abstract: An information processing apparatus includes: a display controller; a letter-size setting section that sets a letter size of a letter string over a plurality of lines which has been entered through an edit screen; and a print controller that prints the letter string in the letter size set by the letter-size setting section. The letter-size setting section can differently set letter sizes of the letter string. When a line feed operation is performed at a head or end of an n-th line through the edit screen, a letter size of the n-th line preset in accordance with a user's designation, the letter-size setting section sets a letter size of one of the n-th line and an (n+1)-th line after the line feed operation so that a length of letter string over the plurality of lines is equal to or shorter than a length of the printable area.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 24, 2022
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoichi OKUMURA
  • Patent number: 9140549
    Abstract: A physical quantity detection element includes a base part, a first connection part and a second connection part respectively extending from the base part in opposite directions to each other along the X-axis, a pair of first drive vibrating arm and second drive vibrating arm and a pair of third drive vibrating arm and fourth drive vibrating arm respectively extending from the first connection part or the second connection part in opposite directions to each other along the Y-axis, a first drive detection vibrating arm and a second drive detection vibrating arm obliquely extending from the first connection part, a third drive detection vibrating arm and a fourth drive detection vibrating arm obliquely extending from the second connection part, and a first detection vibrating arm and a second detection vibrating arm respectively extending from the base part in opposite directions to each other along the Y-axis.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: September 22, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Fumio Ichikawa, Yoichi Okumura, Takayuki Kikuchi
  • Publication number: 20150013540
    Abstract: A system for treating an anaerobically-processed liquid, comprising: a solid-liquid separator provided with a filter submerged in the anaerobically-processed liquid; a gas-liquid separator retaining a filtrate passed through the filter, and having a gas-phase part which contains a gas and is positioned over the filtrate; a filtrate-flow passage connected to a filtrate discharge side of the filter and the gas-phase part of the gas-liquid separator; and a first gas-flow passage connected to the gas-phase part of the gas-liquid separator, and equipped with a depressurization means for depressurizing the gas-phase part.
    Type: Application
    Filed: February 26, 2013
    Publication date: January 15, 2015
    Inventors: Yoichi Okumura, Shin-ichiro Wakahara
  • Publication number: 20130036819
    Abstract: A physical quantity detection element includes a base part, a first connection part and a second connection part respectively extending from the base part in opposite directions to each other along the X-axis, a pair of first drive vibrating arm and second drive vibrating arm and a pair of third drive vibrating arm and fourth drive vibrating arm respectively extending from the first connection part or the second connection part in opposite directions to each other along the Y-axis, a first drive detection vibrating arm and a second drive detection vibrating arm obliquely extending from the first connection part, a third drive detection vibrating arm and a fourth drive detection vibrating arm obliquely extending from the second connection part, and a first detection vibrating arm and a second detection vibrating arm respectively extending from the base part in opposite directions to each other along the Y-axis.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 14, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Fumio ICHIKAWA, Yoichi OKUMURA, Takayuki KIKUCHI
  • Patent number: 7883955
    Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Yoichi Okumura
  • Patent number: 7816867
    Abstract: In a PDP having row electrode pairs and column electrodes formed on the front glass substrate placed parallel to the back glass substrate with a discharge in between, each of the column electrodes faces a central area between adjacent transparent electrodes of the row electrode in the row direction, and is placed in a position closer to the transparent electrode serving as its partner for initiating an address discharge than to the unrelated transparent electrode located on the opposite side of the column electrode.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaki Yoshinari, Yoichi Okumura, Tasuku Ishibashi, Yoichi Shintani
  • Publication number: 20100197091
    Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element separation of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).
    Type: Application
    Filed: April 6, 2010
    Publication date: August 5, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Yoichi OKUMURA
  • Publication number: 20100184247
    Abstract: A semiconductor chip that has a photodiode formed on it, a semiconductor device including the semiconductor chip, and manufacturing methods thereof. A second semiconductor region 11 is formed in light-receiving region R of first semiconductor region 10. First bumps 12 are formed outside light-receiving region R. Second bump 13 is formed in a ring-shape around light-receiving region R between region R and first bumps 12. Semiconductor chip T is assembled on assembly substrate S, and resin layer 30 is formed between chip T and substrate S in the region outside of said light-receiving region R.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoichi Okumura, Ryoichi Kojima
  • Patent number: 7714369
    Abstract: A semiconductor chip that has a photodiode formed on it, a semiconductor device including the semiconductor chip, and manufacturing methods thereof. A second semiconductor region 11 is formed in light-receiving region R of first semiconductor region 10. First bumps 12 are formed outside light-receiving region R. Second bump 13 is formed in a ring-shape around light-receiving region R between region R and first bumps 12. Semiconductor chip T is assembled on assembly substrate S, and resin layer 30 is formed between chip T and substrate S in the region outside of said light-receiving region R.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Yoichi Okumura, Ryoichi Kojima
  • Patent number: 7579858
    Abstract: A semiconductor device is disclosed.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 25, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Yoichi Okumura
  • Patent number: 7524612
    Abstract: An information recording medium has an excellent jitter characteristic with a considerable difference in reflectance between prior to and subsequent to recording. The information recording medium includes a recording layer which contains a material having a reflectance which varies by irradiation of a light beam, on which information is recorded as reflectance variations, and a substrate for supporting the recording layer, the recording layer including a metal nitride as a major component.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: April 28, 2009
    Assignee: Pioneer Corporation
    Inventors: Yasuo Hosoda, Ayumi Mitsumori, Megumi Sato, Masataka Yamaguchi, Tomoaki Izumi, Satoshi Jinno, Yoichi Okumura
  • Publication number: 20090009208
    Abstract: A semiconductor device is disclosed.
    Type: Application
    Filed: September 5, 2008
    Publication date: January 8, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Yoichi Okumura
  • Patent number: 7442972
    Abstract: A semiconductor device is disclosed.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Yoichi Okumura
  • Publication number: 20070108479
    Abstract: A semiconductor device having reduced area occupied by the semiconductor elements that constitute the semiconductor device, and its manufacturing method. Insulating film 12 is formed on substrate 10. First resistance element 18b is formed on insulating film 12. Second resistance element 21b is laminated on first resistance element i8b. In particular, the first resistance element 18b and second resistance element 21b include layers shared with the layer that constitutes the gate electrode (gate electrode 18a) of the field-effect transistor or emitter-forming layer 21a containing an electroconductive impurity and used to form the emitter of the bipolar transistor.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 17, 2007
    Inventor: Yoichi Okumura
  • Publication number: 20070096177
    Abstract: A semiconductor chip that has a photodiode formed on it, a semiconductor device including the semiconductor chip, and manufacturing methods thereof. A second semiconductor region 11 is formed in light-receiving region R of first semiconductor region 10. First bumps 12 are formed outside light-receiving region R. Second bump 13 is formed in a ring-shape around light-receiving region R between region R and first bumps 12. Semiconductor chip T is assembled on assembly substrate S, and resin layer 30 is formed between chip T and substrate S in the region outside of said light-receiving region R.
    Type: Application
    Filed: September 28, 2006
    Publication date: May 3, 2007
    Inventors: Yoichi Okumura, Ryoichi Kojima
  • Publication number: 20060244380
    Abstract: In a PDP having row electrode pairs and column electrodes formed on the front glass substrate placed parallel to the back glass substrate with a discharge in between, each of the column electrodes faces a central area between adjacent transparent electrodes of the row electrode in the row direction, and is placed in a position closer to the transparent electrode serving as its partner for initiating an address discharge than to the unrelated transparent electrode located on the opposite side of the column electrode.
    Type: Application
    Filed: March 22, 2006
    Publication date: November 2, 2006
    Applicant: Pioneer Corporation
    Inventors: Masaki Yoshinari, Yoichi Okumura, Tasuku Ishibashi, Yoichi Shintani