Patents by Inventor Yoichi Oya
Yoichi Oya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070247268Abstract: An inductor element includes a substrate of magnetic material, a coil, and a layer of magnetic material. The coil of conductive material is formed on the substrate. The layer of magnetic material is so formed by aerosol deposition as to enclose the coil on the substrate of magnetic material.Type: ApplicationFiled: February 27, 2007Publication date: October 25, 2007Inventors: Yoichi Oya, Shusaku Yanagawa, Shuichi Oka
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Patent number: 7192801Abstract: The present invention provides a printed circuit board which is capable of air-tightly sealing a functional surface of a device and of preventing excessive stress from acting on the device itself or a conductive bump conjugating the device with a wiring board and a method of fabricating the printed circuit board. The printed circuit board has a device mounted in a hollow formed in a wiring board via a plurality of conductive bumps. In the printed circuit board, a gap is formed between a functional surface of the device and an inner surface of the hollow, and a sealing member is disposed around side surfaces of the device so as to air-tightly isolate the gap and a space within the hollow excepting the gap.Type: GrantFiled: June 23, 2005Date of Patent: March 20, 2007Assignee: Sony CorporationInventor: Yoichi Oya
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Publication number: 20070040281Abstract: To provide a semiconductor device configured that a micro device having a device substrate, a function element provided on the device substrate and having an oscillator or a movable part, first lands provided on a surface of the device substrate by being arranged on its outer circumference portion of the function element, and bumps provided to the first lands is mounted on the circuit board having second lands formed to correspond to the bumps, from the bump formation surface side, so that the bumps and the second lands are electrically connected; on which a sealing resin layer is formed to go round the outer circumference portion of the function element to fix connection portions of the bumps and the second lands, and to seal a clearance between the device substrate and the circuit board; and a cavity portion is formed between the function element and the circuit board.Type: ApplicationFiled: August 18, 2006Publication date: February 22, 2007Inventors: Hirokazu Nakayama, Akihiko Okubora, Yoichi Oya, Hirohito Miyazaki, Kris Baert, Ingrid De Wolf, Piet De Moor, Eric Beyne
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Publication number: 20050239236Abstract: The present invention provides a printed circuit board which is capable of air-tightly sealing a functional surface of a device and of preventing excessive stress from acting on the device itself or a conductive bump conjugating the device with a wiring board and a method of fabricating the printed circuit board. The printed circuit board has a device mounted in a hollow formed in a wiring board via a plurality of conductive bumps. In the printed circuit board, a gap is formed between a functional surface of the device and an inner surface of the hollow, and a sealing member is disposed around side surfaces of the device so as to air-tightly isolate the gap and a space within the hollow excepting the gap.Type: ApplicationFiled: June 23, 2005Publication date: October 27, 2005Inventor: Yoichi Oya
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Patent number: 6949836Abstract: The present invention provides a printed circuit board which is capable of air-tightly sealing a functional surface of a device and of preventing excessive stress from acting on the device itself or a conductive bump conjugating the device with a wiring board and a method of fabricating the printed circuit board. The printed circuit board has a device mounted in a hollow formed in a wiring board via a plurality of conductive bumps. In the printed circuit board, a gap is formed between a functional surface of the device and an inner surface of the hollow, and a sealing member is disposed around side surfaces of the device so as to air-tightly isolate the gap and a space within the hollow excepting the gap.Type: GrantFiled: June 12, 2003Date of Patent: September 27, 2005Assignee: Sony CorporationInventor: Yoichi Oya
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Patent number: 6797890Abstract: A high frequency module device of a thin type, high precision and high functions in which the size and the cost of the package may be diminished. The module device includes a base substrate (2) and a high frequency device layer (4). The base substrate (2) is formed by forming a patterned wiring layer (9) on a first major surface (5a) of a core substrate (5) molded of an organic material exhibiting thermal resistance and high frequency characteristics. The uppermost layer of the base substrate (2) is planarized to form a high frequency device layer forming surface (3). The high frequency device layer portion (4) is formed on the high frequency device layer forming surface (3) by a thin film or thick film forming technique and includes intra-layer passive elements, made up of a resistor (27) and a capacitor (26). The passive elements are supplied with power or signals from the side base substrate.Type: GrantFiled: August 22, 2002Date of Patent: September 28, 2004Assignee: Sony CorporationInventors: Akihiko Okubora, Tsuyoshi Ogawa, Hirokazu Nakayama, Yoichi Oya
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Patent number: 6714422Abstract: A high frequency module device of a thin type, high precision and high functions in which the size and the cost of the package may be diminished. The module device includes a base substrate (2) and a high frequency device layer (4). The base substrate (2) is formed by forming a patterned wiring layer (9) on a first major surface (5a) of a core substrate (5) molded of an organic material exhibiting thermal resistance and high frequency characteristics. The uppermost layer of the base substrate (2) is planarized to form a high frequency device layer forming surface (3). The high frequency device layer portion (4) is formed on the high frequency device layer forming surface (3) by a thin film or thick film forming technique and includes intra-layer passive elements, made up of a resistor (27) and a capacitor (26). The passive elements are supplied with power or signals from the side base substrate.Type: GrantFiled: September 13, 2001Date of Patent: March 30, 2004Assignee: Sony CorporationInventors: Akihiko Okubora, Tsuyoshi Ogawa, Hirokazu Nakayama, Yoichi Oya
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Publication number: 20040000710Abstract: The present invention provides a printed circuit board which is capable of air-tightly sealing a functional surface of a device and of preventing excessive stress from acting on the device itself or a conductive bump conjugating the device with a wiring board and a method of fabricating the printed circuit board. The printed circuit board has a device mounted in a hollow formed in a wiring board via a plurality of conductive bumps. In the printed circuit board, a gap is formed between a functional surface of the device and an inner surface of the hollow, and a sealing member is disposed around side surfaces of the device so as to air-tightly isolate the gap and a space within the hollow excepting the gap.Type: ApplicationFiled: June 12, 2003Publication date: January 1, 2004Inventor: Yoichi Oya
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Publication number: 20020195270Abstract: A high frequency module device of a thin type, high precision and high functions in which the size and the cost of the package may be diminished. The module device includes a base substrate (2) and a high frequency device layer (4). The base substrate (2) is formed by forming a patterned wiring layer (9) on a first major surface (5a) of a core substrate (5) molded of an organic material exhibiting thermal resistance and high frequency characteristics. The uppermost layer of the base substrate (2) is planarized to form a high frequency device layer forming surface (3). The high frequency device layer portion (4) is formed on the high frequency device layer forming surface (3) by a thin film or thick film forming technique and includes intra-layer passive elements, made up of a resistor (27) and a capacitor (26). The passive elements are supplied with power or signals from the side base substrate.Type: ApplicationFiled: August 22, 2002Publication date: December 26, 2002Inventors: Akihiko Okubora, Tsuyoshi Ogawa, Hirokazu Nakayama, Yoichi Oya
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Patent number: 6469393Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress.Type: GrantFiled: April 14, 1999Date of Patent: October 22, 2002Assignee: Sony CorporationInventor: Yoichi Oya
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Publication number: 20020075106Abstract: A high frequency module device of a thin type, high precision and high functions in which the size and the cost of the package may be diminished. The module device includes a base substrate (2) and a high frequency device layer (4). The base substrate (2) is formed by forming a patterned wiring layer (9) on a first major surface (5a) of a core substrate (5) molded of an organic material exhibiting thermal resistance and high frequency characteristics. The uppermost layer of the base substrate (2) is planarized to form a high frequency device layer forming surface (3). The high frequency device layer portion (4) is formed on the high frequency device layer forming surface (3) by a thin film or thick film forming technique and includes intra-layer passive elements, made up of a resistor (27) and a capacitor (26). The passive elements are supplied with power or signals from the side base substrate.Type: ApplicationFiled: September 13, 2001Publication date: June 20, 2002Inventors: Akihiko Okubora, Tsuyoshi Ogawa, Hirokazu Nakayama, Yoichi Oya
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Publication number: 20020058356Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress.Type: ApplicationFiled: August 3, 2000Publication date: May 16, 2002Inventor: Yoichi Oya
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Publication number: 20010054753Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress.Type: ApplicationFiled: April 14, 1999Publication date: December 27, 2001Inventor: YOICHI OYA