Patents by Inventor Yoichi Takayanagi

Yoichi Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151133
    Abstract: According to the present embodiment, a server device comprises a communicator, a determiner, and a control operation part. The communicator sequentially receives a plurality of first packets each including a same first signal with respect to each of different pieces of connection information via a network. The determiner determines whether the first signal included in each of the first packets has been already received. The control operation part generates a second signal corresponding to the first signal when the first signal is determined not to have been already received based on the determination.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Naoya OHNISHI, Hiroshi Nakatani, Tatsuma Hirano, Hiroki Matsuyama, Yoichi Takayanagi, Motohiko Okabe
  • Publication number: 20250150330
    Abstract: According to the present embodiment, a transmission/reception device includes a connecter and a determiner. The connecter is configured to establish a communication link with a communication counterpart via a network. The determiner is a determiner configured to determine a state of the communication link and to cause the connector to switch the communication link to be another communication link when the communication link is in a predetermined state.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Tatsuma HIRANO, Hiroki MATSUYAMA, Naoya OHNISHI, Hiroshi NAKATANI, Yoichi TAKAYANAGI, Motohiko OKABE
  • Patent number: 8281203
    Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Murakami, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Publication number: 20120030402
    Abstract: A PCI Express TLP processing circuit (10) comprises: a plurality of reception processing sections (2a1); a transmission processing section (2b); and a multiplexer (2c1) that performs transmission to the transmission processing section, selecting one of the reception processing sections; and at least a reception processing section comprises: a redundancy code generating circuit (12); an LCRC/sequential number detection circuit (13); a buffer memory (14); a packet control circuit section (16) that controls transmission for normal transmission to the transmission destination of the TLP in question or for nullifying transmission; and the transmission processing section comprises: a sequential number generating circuit (19); an LCRC generating circuit (20) and a relay circuit error detection circuit (21), whereby data integrity of the transmitted TLP can be guaranteed.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki MURAKAMI, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Publication number: 20100251055
    Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Murakami, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Patent number: 6598108
    Abstract: An integrated controller, including a plurality of controllers, each of the controllers executing a different program, and an integrator configured to imaginarily integrate the controllers as a single controller.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: July 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Ashida, Yoichi Takayanagi