Patents by Inventor Yoichi Takegawa
Yoichi Takegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070267680Abstract: A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors are provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.Type: ApplicationFiled: May 16, 2007Publication date: November 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukinori Uchino, Muneaki Maeno, Yoichi Takegawa, Hisato Oyamatsu
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Patent number: 7276750Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.Type: GrantFiled: August 20, 2004Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kido, Hideaki Aochi, Toshiharu Tanaka, Ryota Katsumata, Hideki Inokuma, Yoichi Takegawa
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Patent number: 6960514Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: March 18, 2004Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Publication number: 20050101094Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.Type: ApplicationFiled: August 20, 2004Publication date: May 12, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kido, Hideaki Aochi, Toshiharu Tanaka, Ryota Katsumata, Hideki Inokuma, Yoichi Takegawa
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Publication number: 20040173858Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: ApplicationFiled: March 18, 2004Publication date: September 9, 2004Inventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Patent number: 6746933Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: October 26, 2001Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Patent number: 6632723Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.Type: GrantFiled: April 26, 2002Date of Patent: October 14, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama
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Patent number: 6495876Abstract: A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.Type: GrantFiled: June 30, 2000Date of Patent: December 17, 2002Assignee: International Business Machines CorporationInventors: Gary Bronner, Ramachandra Divakaruni, Yoichi Takegawa
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Publication number: 20020160581Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.Type: ApplicationFiled: April 26, 2002Publication date: October 31, 2002Inventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama