Abstract: A communication network includes a plurality of stations interconnected by a coaxial cable. Communication among stations is effected in packet form, the packets being located in blocks repeated periodically in time. At least one station may be provided with composing circuits effecting interconnection among several stations by linking transmitters and receivers of different stations. Alternatively, a separate central station acts to link an originating station with requested other stations in a manner such that channel connection among the linked stations is effected by a single packet.

Abstract: For coupling a digital signal between two asynchronous transmission paths, an asynchronous connecting device includes a serial-to-parallel converter for converting the digital signal into parallel words, a first latch for latching the parallel words at a rate synchronized to the first transmission path, a second latch for latching the output of the first latch at a rate synchronized to the second transmission path, and a parallel-to-serial converter for converting the output of the second latch into a serial digital signal to be transmitted along the second transmission path. It is preferable that the sampling rate of the second latch be higher than that of the first latch, and it is also possible to smooth the second latch output prior to converting it to serial data.

Abstract: In a pocket switching communications system of the type in which each station sends its packet into an unoccupied block within a frame, the retransmission interval is determined by generating a random number, weighting the random number in accordance with the number of collisions which the station has encountered since it first requested transmission and/or the degree of congestion monitored in the frame in which the most recent collision occurred. The retransmission interval is then determined in accordance with the weighted number.

Abstract: A communication system includes a plurality of digital signal transmission systems each connected to the next by a repeater installation. Signal packets travelling from a station in one system to a station in another adjacent system are picked out by a repeater station and stored in a buffer memory. The contents of the memory are compiled into a packet for transmission to the other system, with an address designating the station of the other system, and are inserted into an empty block or blocks of a periodically repeated frame of the other system with a waiting time of less than one complete frame.

Abstract: In a digital signal transmission system for effecting time-division multiplexing/circuit switching transmission of data in the form of packets by means of telecommunication cable, a packet configuration and line connection control data inserted in the packets are improved. In phases of the establishment/termination of a call, line connection control data of the overhead field are inserted as repeated at least one time into the data field. At least one set of line connection control data of the overhead field contains a parity bit. A receiving station reads the line connection control data in the overhead field and the data field of a received packet, and determines the overhead data by the principle of decision by majority. After completion of establishment of a call, the receiving station takes in the transferred data out of a block on the basis of a positional information, for example, a number of the block.

Abstract: A modulated signal level detecting circuit comprising a synchronized detector 1 of the modulated input signal, a phase-locked loop 5, 14, 16 connected to the input signal for providing a reproduced carrier wave of the input signal, a switch 21 included in the phase-locked loop, and a signal level detecting circuit 22, 23 for detecting the level of the unmodulated signal and opening the switch and thereby breaking the loop when this level exceeds a fixed limit.

Abstract: A multistation digital communication network of the type wherein station packet signals are transmitted during periodically repeated block times, a plurality of blocks forming a frame, each block time repeating once per frame, the first block of a frame being the master block. Multiple, contiguous empty blocks within a single frame are produced by locating all signal carrying frame blocks and packing them one against the other beginning with the master frame, to thereby form multiple, contiguous signal carrying or used blocks beginning from and including the master block. The remainder of the frame blocks are then contiguous empty blocks capable of receiving new packet signals, several blocks in length. Each station of the multistation network is provided with circuitry for accomplishing the block packing technique and for determining the first and last contiguous empty frame blocks.

Abstract: In a time division multiplex cable communication system, each station transmits with its packet a designation code representing the propagation delay time between that station and a reference position on the cable to facilitate calculation of the proper transmission timing.

Abstract: In a multi station communication network wherein interstation communications are carried out by transmitting packets of information in selected blocks of repeating time division multiplex frames, the calling station reserves a block for transmission of an answer packet from the called station.

Abstract: A multipoint communication system has a plurality of stations connected to a cable. All stations transmit data in packets of information within blocks subdivided in a frame which has a repetitive period. Frame and block synchronization is based on a key station's packet being transmitted within the first block of each frame. Other stations synchronize their frame and block timings to the key station packet. Any station in the system can take over as the key station.

Abstract: The upward and downward transitions of an input signal are independently detected with undirectional hysteresis in opposite directions. The detection signals are then combined to provide a level crossing detection signal having no time lag and immune to small noise signals.

Abstract: A data transmitting system where transmission in packet form takes place between several stations includes an encoder converting signals into a transmission waveform where the low frequency components are significantly attenuated. A sub-signal, notably a voice signal from a telephone set is multiplied on the low frequency region and also transmitted between the stations.

Abstract: A digital signal combining circuit for a diversity receiver for digital communication comprises buffer memories (16) for memorizing digital signal sequences produced by receiver units (11, 12), respectively, and an APC loop (26-39) for locking the phases of read-out clocks for simultaneously reading the memories to an averaged phase of the digital signal sequences. No code error appears in an output signal of the receiver provided that the phase difference between two of the digital signal sequences from which the output signal is selected, is less than m bit periods, where m represents the number of memory cells of each buffer memory.

Abstract: A demodulator for PSK-FM double modulated carrier signals in which the carrier signal is 2.sup.N phase modulated by a main signal and frequency modulated by a sub-signal. A clock component is extracted from the received double-modulated carrier signal and the carrier signal sampled in accordance therewith. The amplitude of the output of the sampling gate is limited prior to frequency multiplication by 2.sup.N. A frequency modulated component is then demodulated from the multiplied signal.

Abstract: A bit error detecting circuit for a digital signal transmission line of the type having a main decision circuit and a sub-decision circuit is disclosed. The purpose of the sub-decision circuit is to provide a prediction of a fault in the transmission, and this is accomplished without being adversely effected by a drift in the threshold level. A clock recovery circuit is responsive to the input digital signal to produce a clock signal which is supplied to both the main decision circuit and the sub-decision circuit and to a pattern generating circuit such as a binary counter. The main decision circuit decides the binary code of the input digital signal with respect to a first reference level. The binary code pattern from the pattern generating circuit is added to the input digital signal and the sum supplied to the sub-decision circuit which decides the binary code of the sum with respect to a second reference level.

Abstract: An FSK demodulator is provided with an AFC circuit. The AFC circuit is a negative feedback loop having at least n stable points corresponding to n-level transmitting frequencies. The cut-off frequency of the negative feedback loop is selected higher than the cut-off frequency of the low frequency components from the n-level signals containing a D.C. component which are used to generate the transmitting frequencies.

Abstract: A code converter circuit in a digital transmission system in which two mutually-synchronized digital signals are transmitted through a pair of transmission paths is disclosed. The transmission paths are characterized by the possibility of the terminal-to-terminal correspondence between input and output sides of the transmission paths being reversed. The code converter circuit includes an encoder on the input side of the transmission paths and a decoder on the output side of the transmission paths. The encoder comprises a modulo-2 adder and a switching circuit for selectively switching the input digital signals or the adder output signals to the transmission paths. The decoder comprises a modulo-2 subtractor and a switching circuit for selectively switching the digital signals from the transmission paths or the subtractor output signals to reproduce the transmitted digital signals.

Abstract: A synchronized carrier recovery circuit for a PSK modulated signal includes a plurality of phase detectors supplied with the PSK input signal and phase shifted outputs from a voltage controlled oscillator. The detector outputs are rectified and alternately coupled to a pair of adders whose outputs feed a complimentary subtractor. The detector outputs are also converted to digital form and fed to an Exclusive OR circuit, whose output couples the appropriate subtractor outputs to the VCO to achieve phase locked synchronization.

Abstract: The frame holding time can be materially extended without increasing the counter size by insertion of a delay circuit and an AND gate between the framing detector and hunting means. Hunting operation is performed under control of the logical AND of the detector output and its retarded counterpart. The frame holding time obtained in the present invention corresponds to the sum of the retardation time of the delay circuit and the frame holding time of the conventional device.

Abstract: A baseband signal switching arrangement for the diversity reception of pulse-modulated microwaves is capable of selecting anyone of respective demodulated baseband digital signals without causing any bit errors in the output. The baseband signal switching arrangement includes a digital signal gate switch for selecting one of a plurality of digital signals and a clock signal gate switch for selecting a corresponding one of a plurality of clock signals extracted respectively from the digital signals. A delay circuit is provided for delaying the clock signal selected by the clock signal gate switch, and a control signal read-out circuit is arranged to be fed with the output of the delay circuit to read out a switching control signal so that the digital signal and clock signal gate switches are controlled simultaneously by the output of the control signal read-out circuit.