Patents by Inventor Yoichiro Kawamura

Yoichiro Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141504
    Abstract: There is provided a steel sheet for cans including, on a surface of a steel sheet, a chromium metal layer and a hydrated chromium oxide layer stacked in this order from the steel sheet side. The chromium metal layer has a coating weight of 50 to 200 mg/m2, and the hydrated chromium oxide layer has a coating weight of 3 to 30 mg/m2 in terms of chromium amount. The chromium metal layer includes a base portion of flat plate shape and granular protrusions provided on the base portion. At least 20% of the granular protrusions has a circularity C of 0.85 or less. The circularity C is expressed by C=4?A/U2, when the outer perimeter of a projection image of a granular protrusion is represented by U, and the area thereof is represented by A.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 2, 2024
    Applicant: JFE Steel Corporation
    Inventors: Yuto Kawamura, Yusuke Nakagawa, Yoichiro Yamanaka, Jialin Wang, Shuhei Kozu
  • Patent number: 9040843
    Abstract: A multilayered printed circuit board including a substrate, a multilayered structure formed on the substrate and including multiple conductor circuits and multiple interlaminar resin insulating layers, and a stack-via structure having multiple via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure. The interlaminar resin insulating layers include an outermost interlaminar resin insulating layer forming an outermost layer of the interlaminar resin insulating layers and having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 26, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Yukihiko Toyoda, Yoichiro Kawamura, Tomoyuki Ikeda
  • Patent number: 8832935
    Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 16, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8624132
    Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 7, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8525041
    Abstract: A wiring board has a substrate, a conductive pattern formed over the substrate, and an electronic component mounted to the substrate and having an electrode. The electrode of the electronic component is connected to the conductive pattern through a via hole. The thickness of the electrode of the electronic component is made less than the thickness of the conductive pattern.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: September 3, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Keisuke Shimizu, Yoichiro Kawamura
  • Publication number: 20130008701
    Abstract: A multilayered printed circuit board including a substrate, a multilayered structure formed on the substrate and including multiple conductor circuits and multiple interlaminar resin insulating layers, and a stack-via structure having multiple via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure. The interlaminar resin insulating layers include an outermost interlaminar resin insulating layer forming an outermost layer of the interlaminar resin insulating layers and having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: IBIDEN CO., LTD.
    Inventors: Yukihiko TOYODA, Yoichiro Kawamura, Tomoyuki Ikeda
  • Patent number: 8324512
    Abstract: A multilayered printed circuit board including a substrate, a multilayered structure built thereon and having conductor circuits and interlaminar resin insulating layers in an alternate fashion, and one or more stack-via structures including via-holes stacked one another and electrically connected to the conductor circuits through the insulating layers. Each of the via-holes includes a land portion formed on a respective one of the insulating layers and a filled via structure portion filling an opening of the respective one of the insulating layers with a metal layer such that the via-holes are stacked one another immediately above the filled via structure portion of each via-hole, the via-holes include the outermost layer via-hole in the outermost layer of the insulating layers, and one or more via-holes have the land portion having the land diameter which is larger than the land diameter of the land portion of the outermost layer via-hole.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 4, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yukihiko Toyoda, Yoichiro Kawamura, Tomoyuki Ikeda
  • Patent number: 8222539
    Abstract: A wiring board has a conductive pattern, an electronic component connected to the conductive pattern by means of a via hole, and a substrate where the electronic component is built into. The connection interface between the via hole and the electronic component inclines toward the connection interface between the via hole and the conductive pattern.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: July 17, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Keisuke Shimizu
  • Patent number: 8198546
    Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: June 12, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8030579
    Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 4, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yukihiko Toyoda, Yoichiro Kawamura, Tomoyuki Ikeda
  • Patent number: 8022314
    Abstract: A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 20, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8017875
    Abstract: A printed wiring board includes a wiring substrate, one or more conductor circuits provided on the wiring substrate, a solder resist layer provided on a surface of the wiring substrate and having multiple openings, the openings exposing multiple parts of the conductor circuits forming multiple conductor pads for mounting electronic parts, and multiple solder bumps formed on the conductor pads, respectively. The conductor pads are aligned at a pitch of about 200 ?m or less, and a ratio W/D of a diameter W of the solder bumps to an opening diameter D of the openings formed in the solder resist layer is about 1.05 to about 1.7.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 13, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Publication number: 20110214915
    Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 ?m or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
    Type: Application
    Filed: May 17, 2011
    Publication date: September 8, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro KAWAMURA, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8003897
    Abstract: A printed wiring board includes a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 ?m or less.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 23, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 8001683
    Abstract: This invention provides a solder ball loading apparatus which enables fine solder balls to be loaded on pads while void is blocked from being caught into bump upon reflow. Inactive gas is supplied and the inactive gas is sucked from a loading cylinder located above a ball arrangement mask so as to gather solder balls. The gathered solder balls are rolled on the ball arrangement mask by moving the loading cylinder horizontally and the solder balls are dropped onto connecting pads on a multilayer printed wiring board through openings in the ball arrangement mask. Oxidation of the solder balls and mixture of voids upon reflow are prevented by loading the solder balls in the atmosphere of inactive gas.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 23, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoichiro Kawamura, Katsuhiko Tanno
  • Publication number: 20110108311
    Abstract: A multilayered printed circuit board including a substrate, a multilayered structure built thereon and having conductor circuits and interlaminar resin insulating layers in an alternate fashion, and one or more stack-via structures including via-holes stacked one another and electrically connected to the conductor circuits through the insulating layers. Each of the via-holes includes a land portion formed on a respective one of the insulating layers and a filled via structure portion filling an opening of the respective one of the insulating layers with a metal layer such that the via-holes are stacked one another immediately above the filled via structure portion of each via-hole, the via-holes include the outermost layer via-hole in the outermost layer of the insulating layers, and one or more via-holes have the land portion having the land diameter which is larger than the land diameter of the land portion of the outermost layer via-hole.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 12, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Yukihiko TOYODA, Yoichiro KAWAMURA, Tomoyuki IKEDA
  • Publication number: 20110061232
    Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
  • Patent number: 7866529
    Abstract: A solder ball loading unit for loading a solder balls to be turned to a solder bumps on a connection pad of a printed wiring board, including a ball arranging mask having a plurality of openings corresponding to the connection pad of the printed wiring board, a cylinder member located above the ball arranging mask for gathering the solder balls just below the opening portion by sucking air from the opening portion, and a moving mechanism for moving the cylinder member in the horizontal direction, the moving mechanism moving the solder balls gathered on the ball arranging mask by moving the cylinder member and dropping the solder balls onto the connection pads of the printed wiring board through the opening in the ball arranging mask.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: January 11, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Atsunori Sumita, Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Isao Tsuchiya, Yoshiyuki Mabuchi, Osamu Kimura
  • Patent number: 7823762
    Abstract: A solder ball is loaded on a bump having a small height (FIG. 5(B)) and the height of the bump is intensified by melting the solder ball by heating with laser (FIG. 5(C)). Thus, the heights of the bumps are adjusted within a requested allowable range. Because the bump is not removed by heating when the height of the low bump is intensified, the printed wiring board is not subjected to local heat history thereby intensifying reliability of the bump of a printed wiring board.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: November 2, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yoichiro Kawamura, Katsuhiko Tanno, Masanori Iriyama, Sho Akai
  • Patent number: RE44251
    Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: June 4, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Yoichiro Kawamura, Yoji Mori