Abstract: A CPU decodes MP3 data, stores it in a buffer memory, and issues a transfer instruction. A predetermined time period is required for the CPU to issue a first transfer instruction after turning-on of power supply. A DMA controller transfers data stored in the buffer memory in response to the transfer instruction. A power supply control unit turns off power supply to a first area when a time period for completing transfer of current data awaiting transfer reaches a first time period longer than the predetermined time period, according to an amount of data awaiting transfer in the buffer memory, and then turns on the power supply to the first area when the time period for completing the transfer of the current data awaiting transfer reaches a second time period which is equal to or longer than the predetermined time period and is shorter than the first time period.