Abstract: A semiconductor device includes first and second voltage control lines for a first memory block and third and fourth voltage control lines for a second memory block, for driving gate lines for memory transistors; a first decoder driving the first and third voltage control lines; a second decoder driving the second and fourth voltage control lines; and a control circuit controlling a voltage for the first and second decoders. The control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and a third voltage between the first and second voltages, and the second voltage to the second decoder, before writing operation; and supplies the first voltage and the third voltage to the first decoder and a fourth voltage between the third and second voltages, and a fifth voltage lower than the second voltage to the second decoder, in the writing operation.

Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.

Abstract: To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.

Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.

Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.

Abstract: To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.

Abstract: A semiconductor device includes first and second voltage control lines for a first memory block and third and fourth voltage control lines for a second memory block, for driving gate lines for memory transistors; a first decoder driving the first and third voltage control lines; a second decoder driving the second and fourth voltage control lines; and a control circuit controlling a voltage for the first and second decoders. The control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and a third voltage between the first and second voltages, and the second voltage to the second decoder, before writing operation; and supplies the first voltage and the third voltage to the first decoder and a fourth voltage between the third and second voltages, and a fifth voltage lower than the second voltage to the second decoder, in the writing operation.

Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.

Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).

Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).

Abstract: The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.

Abstract: The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.

Abstract: A control circuit generates burn-in test signals and a signal on the basis of an address for causing transition of a semiconductor memory device to a burn-in test mode to output the signals to a predecoder. The predecoder outputs signals for selecting even-numbered word lines and signals for causing odd-numbered word lines to be in a non-selected state on the basis of the burn-in test signals at H level and further outputs signals for causing even-numbered word lines to be in a non-selected state and signals for selecting odd-numbered word lines on the basis of the burn-in test signals at H level. As a result, stresses can be effectively applied by the burn-in test.

Abstract: A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.

Abstract: A comparator of a synchronous SRAM includes: n+1 EX-OR gates for detecting whether or not n+1 signals included in an address signal inputted in a cycle and n+1 signals included in an address signal inputted in the next cycle coincide with each other; and wired OR gates receiving output signals of the n+1 EX-OR gates. Accordingly, a detecting speed is faster than in a prior art practice where an OR gate is constituted of NOR gates and NAND gates at multiple stages.

Abstract: During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.

Abstract: A control circuit generates burn-in test signals and a signal on the basis of an address for causing transition of a semiconductor memory device to a burn-in test mode to output the signals to a predecoder. The predecoder outputs signals for selecting even-numbered word lines and signals for causing odd-numbered word lines to be in a non-selected state on the basis of the burn-in test signals at H level and further outputs signals for causing even-numbered word lines to be in a non-selected state and signals for selecting odd-numbered word lines on the basis of the burn-in test signals at H level. As a result, stresses can be effectively applied by the burn-in test.

Abstract: A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.

Abstract: A comparator of a synchronous SRAM includes: n+1 EX-OR gates for detecting whether or not n+1 signals included in an address signal inputted in a cycle and n+1 signals included in an address signal inputted in the next cycle coincide with each other; and wired OR gates receiving output signals of the n+1 EX-OR gates. Accordingly, a detecting speed is faster than in a prior art practice where an OR gate is constituted of NOR gates and NAND gates at multiple stages.

Abstract: During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.