Abstract: An ion implantation method includes irradiating a wafer having a first temperature with a first ion beam such that a predetermined channeling condition is satisfied and irradiating the wafer having a second temperature different from the first temperature with a second ion beam such that the predetermined channeling condition is satisfied, after the irradiation of the first ion beam.

Abstract: An ion implantation method includes irradiating a wafer having a first temperature with a first ion beam such that a predetermined channeling condition is satisfied and irradiating the wafer having a second temperature different from the first temperature with a second ion beam such that the predetermined channeling condition is satisfied, after the irradiation of the first ion beam.

Abstract: An ion implantation method includes irradiating a wafer having a first temperature with a first ion beam such that a predetermined channeling condition is satisfied and irradiating the wafer having a second temperature different from the first temperature with a second ion beam such that the predetermined channeling condition is satisfied, after the irradiation of the first ion beam.

Abstract: An ion implantation method includes: irradiating a wafer arranged to meet a predetermined plane channeling condition with an ion beam; measuring a predetermined characteristic on a surface of the wafer irradiated with the ion beam; and evaluating an implant angle distribution of the ion beam by using a result of measurement of the characteristic. The wafer may be arranged so as to include a channeling plane parallel to a predetermined reference plane parallel to a reference trajectory direction of the ion beam incident on the wafer and not to include a channeling plane perpendicular to the reference plane and parallel to the reference trajectory direction.

Abstract: An ion implantation method for scanning an ion beam reciprocally in an x direction and moving a wafer reciprocally in a y direction to implant ions into the wafer is provided. The method includes: irradiating a first wafer arranged to meet a predetermined plane channeling condition with the ion beam and measuring resistance of the first wafer irradiated with the ion beam; irradiating a second wafer arranged to meet a predetermined axial channeling condition with the ion beam and measuring resistance of the second wafer irradiated with the ion beam; and adjusting an implant angle distribution of the ion beam by using results of measuring the resistance of the first and second wafers.

Abstract: An ion implantation method includes: irradiating a wafer arranged to meet a predetermined plane channeling condition with an ion beam; measuring a predetermined characteristic on a surface of the wafer irradiated with the ion beam; and evaluating an implant angle distribution of the ion beam by using a result of measurement of the characteristic. The wafer may be arranged so as to include a channeling plane parallel to a predetermined reference plane parallel to a reference trajectory direction of the ion beam incident on the wafer and not to include a channeling plane perpendicular to the reference plane and parallel to the reference trajectory direction.

Abstract: An ion implantation method for scanning an ion beam reciprocally in an x direction and moving a wafer reciprocally in a y direction to implant ions into the wafer is provided. The method includes: irradiating a first wafer arranged to meet a predetermined plane channeling condition with the ion beam and measuring resistance of the first wafer irradiated with the ion beam; irradiating a second wafer arranged to meet a predetermined axial channeling condition with the ion beam and measuring resistance of the second wafer irradiated with the ion beam; and adjusting an implant angle distribution of the ion beam by using results of measuring the resistance of the first and second wafers.

Abstract: According to one embodiment, a light emitting device includes first and second plate electrodes, a light emitting element and an insulator. The first plate electrode includes first and second major surfaces. The second plate electrode includes third and fourth major surfaces. The light emitting element is placed between the first surface and third major surfaces. The light emitting element includes a semiconductor stacked body having a fifth major surface and a sixth major surface, a first electrode and a second electrode. The semiconductor stacked body includes a light emitting layer. Optical axis is made perpendicular to a side surface of the semiconductor stacked body. The insulator is provided in contact with the first and second plate electrodes and including a window. The light beam is enabled to pass through the window and to be emitted outward.

Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.

Abstract: A semiconductor device having a FIN type transistor including a FIN-shape semiconductor portion improved for reliability by suppressing scattering of the characteristics of the FIN-shape transistor by decreasing a difference between impurity concentration at an upper surface and impurity concentration on a lateral side of the FIN-shape semiconductor portion, in which a pad insulating film at a thickness of about 2 to 5 nm is formed to the upper surface of the FIN-shape semiconductor portion, cluster ions are implanted to one lateral side of the FIN-shape semiconductor portion from an oblique direction at a first implantation angle ?1 and then cluster ions are implanted to another lateral side of the FIN-shape semiconductor portion from an oblique direction at a second implantation angle ?2 in symmetrical with the first implantation angle ?1 and, subsequently, the cluster ions implanted to the FIN-shape semiconductor portion 10 are activated to form a diffusion region that forms a portion of a source region an

Abstract: A light emitting device includes a first light source, an optical waveguide body, a light emitting layer and a first reflection layer. The optical waveguide body includes a first end surface to which light from the first light source is injected, and a second end surface opposed to the first end surface and provided in a light guiding direction of the light. The light emitting layer includes, along the light guiding direction, phosphor particles capable of absorbing the light and emitting wavelength converted light or a light diffusing agent diffusing the light. The first reflection layer is provided on the second end surface and is capable of reflecting part of the light guided in the optical waveguide body. Diffused light from the light emitting layer is emitted to outside of the optical waveguide body.

Abstract: A light emitting device includes a light source capable of emitting emission light, a first phosphor layer and an optical waveguide. A first phosphor layer has at least a first surface and a second surface on an opposite side of the first surface, extends in a light guiding direction, and is capable of absorbing the emission light and emitting first wavelength converted light having a longer wavelength than the emission light. The optical waveguide has a reflector. And the optical waveguide has an input surface of the emission light, a reflection surface being in contact with the first surface of the first phosphor layer and provided on a surface of the reflector, and an output surface spaced from the first phosphor layer. The reflection surface and the output surface extend in the light guiding direction.

Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.

Abstract: A semiconductor device having a FIN type transistor including a FIN-shape semiconductor portion improved for reliability by suppressing scattering of the characteristics of the FIN-shape transistor by decreasing a difference between impurity concentration at an upper surface and impurity concentration on a lateral side of the FIN-shape semiconductor portion, in which a pad insulating film at a thickness of about 2 to 5 nm is formed to the upper surface of the FIN-shape semiconductor portion, cluster ions are implanted to one lateral side of the FIN-shape semiconductor portion from an oblique direction at a first implantation angle ?1 and then cluster ions are implanted to another lateral side of the FIN shape semiconductor portion from an oblique direction at a second implantation angle ?2 in symmetrical with the first implantation angle ?1 and, subsequently, the cluster ions implanted to the FIN-shape semiconductor portion 10 are activated to form a diffusion region that forms a portion of a source region an

Abstract: A hollow type planar illuminating device having uniform luminance distribution over the entire light emitting is described. A reflecting surface member is arranged on the bottom side of a hollow unit case, a light emitting surface member is arranged on the side facing the reflecting surface member of the unit case, and a space sandwiched between the reflecting surface member and the light emitting surface member of the unit case forms a hollow light guide space. An LED light source unit emits light into the hollow light guide space with a light collecting lens arranged between the LED light source unit and an end surface of the hollow light guide space. The light collecting lens reduces the directivity angle of light emitted from the LED light source unit in the device thickness direction.

Abstract: Provided is a hollow type planar illuminating device having uniform luminance distribution over the entire light emitting surface. A reflecting surface member (2) is arranged on the bottom side of a hollow unit case (1), a light emitting surface member (3) is arranged on the side facing the reflecting surface member of the unit case, and a space sandwiched between the reflecting surface member and the light emitting surface member of the unit case is permitted to be a hollow light guide space (10). An LED light source unit (5) wherein many LEDs are mounted in a row on a wiring board is arranged adjacent to the both sides or one side of the hollow light guide space so that light is emitted to the hollow light guide space. Between the LED light source unit and an end surface of the hollow light guide space, a light collecting lens (9) is arranged. The light collecting lens reduces the directivity angle of light emitted from the LED light source unit in the device thickness direction.

Abstract: A light reflection surface member (2) is arranged on the bottom surface of a hollow unit case (1), a light emitting surface member (3) is arranged on the upper surface side of the unit case to face the light reflection surface member, and a hollow light guide region (10) is formed by being sandwiched by the light reflection surface member and the light emitting member. On the side surface of the unit case, an LED light source (5) is arranged. The LED light source has many LEDs (7R, 7B, 7G) in rows, and each LED emits single color light of red or green or blue. On two strips of light reflection surface member in the unit case (1), a color sensor is arranged for measuring illuminance of each color light entered the hollow light guide region from the LED light source (5).

Abstract: A surface light-emitting device is disclosed, in which a plurality of spot light sources are arranged along the side surface of a housing of the device, and the light emitted from the spot light sources located at the end portions of the spot light source sequence emits a lower light flux than the average light flux of the light emitted from the other spot light sources. The spot light source sequence is, for example, an LED array including an alignment of light-emitting diodes (LEDs). The LED array includes two groups of LED elements arranged in a predetermined repetitive pattern from one and the other ends, respectively, of the LED array, and at least an LED emitting low light flux is arranged at a predetermined position in the vicinity of the center of the array. As a result, the requirement for a reduced thickness and a narrower frame can be met, while at the same time producing the white light of uniform chromaticity over the whole light-emitting surface.

Abstract: A method of producing ultra shallow junctions (104) for PMOS transistors, which eliminates the need for pre-amorphization implants, is disclosed. The method utilizes dopant species, such as cluster ions, e.g., octadecaborane, B18H22. In accordance with the present invention, the pre-amorphizing step may be eliminated, greatly reducing cost per processed wafer. An appropriate process sequence has been suggested to take advantage of cluster ion implantation for PMOS manufacturing. In addition, the novel use of tilted implants for the source/drain extension and for pocket implants has been described.