Patents by Inventor Yoji Nakata

Yoji Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787878
    Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Nagai, Tomoharu Mametani, Yoji Nakata, Shigenori Kido, Takeshi Kishida, Akinori Kinugasa, Hiroaki Nishimura, Jiro Matsufusa
  • Patent number: 6770557
    Abstract: In order to provide a method of fabricating a semiconductor device improved to be capable of attaining high reliability of wiring, a plug material is deposited on a semiconductor substrate to fill up a contact hole. The plug material is etched back thereby forming a plug in the contact hole. The surface of a cavity defined in the plug is covered with an insulator film. A metal wire is formed on the interlayer isolation film to be in contact with the plug.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Yoji Nakata
  • Patent number: 6744143
    Abstract: A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Jiro Matsufusa, Tomoharu Mametani, Takeshi Kishida, Yoji Nakata, Yukihiro Nagai, Hiroaki Nishimura, Akinori Kinugasa, Shigenori Kido
  • Patent number: 6635563
    Abstract: Precisely forming a fine resist pattern on a stopper film of silicon nitride, in a method of manufacturing a multi-layer interconnection structure which uses the stopper film. A silicon nitride film forming step is a step to select a thickness of a silicon nitride film to thereby reduce reflection light of an excimer laser which impinges upon a photoresist layer on the silicon nitride film from the back surface of the photoresist layer.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: October 21, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoji Nakata
  • Publication number: 20030008498
    Abstract: In order to provide a method of fabricating a semiconductor device improved to be capable of attaining high reliability of wiring, a plug material is deposited on a semiconductor substrate to fill up a contact hole. The plug material is etched back thereby forming a plug in the contact hole. The surface of a cavity defined in the plug is covered with an insulator film. A metal wire is formed on the interlayer isolation film to be in contact with the plug.
    Type: Application
    Filed: April 25, 2002
    Publication date: January 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoji Nakata
  • Publication number: 20020098674
    Abstract: Precisely forming a fine resist pattern on a stopper film of silicon nitride, in a method of manufacturing a multi-layer interconnection structure which uses the stopper film.
    Type: Application
    Filed: September 20, 2001
    Publication date: July 25, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoji Nakata
  • Patent number: 6337268
    Abstract: A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: January 8, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenori Kido, Jiro Matsufusa, Tomoharu Mametani, Yoji Nakata, Takeshi Kishida, Yukihiro Nagai, Akinori Kinugasa, Hiroaki Nishimura
  • Patent number: 6313005
    Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: November 6, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeshi Kishida, Akinori Kinugasa, Yoji Nakata, Tomoharu Mametani, Shigenori Kido, Yukihiro Nagai, Hiroaki Nishimura, Jiro Matsufusa