Abstract: A device for converting an analog signal into a corresponding N-bit digital signal (A/D converter) of a parallel comparison type is disclosed having a 2.sup.N-M number of M-bit encoders, a single N-bit encoder, and error suppression circuits, a block indicating signal on a block indicating line belonging to each M-bit encoder serving as an output inhibit signal for one of the other error suppression circuits connected to the M-bit encoder in one lower order for higher order) with respect to the corresponding M-bit encoder, and the block indicating line of each M-bit encoder being connected to an output terminals of one of the comparators in a lowest order (or highest order) or a few comparators in the comparator group to which the corresponding M-bit encoder is connected.

Abstract: An improved circuit for compensating an input/output characteristic linearity of a parallel comparison type analog-to-digital converter which reduces a wasteful consumption of current in the linearity compensation circuit. In the improved linearity compensation circuit, a dummy circuit having the same construction as a bias circuit of each comparator of the A/D converter is installed for providing a current I.sub.E which is an amplification of an input current by means of the input circuit of each comparator, a first current multiplier is installed for providing a multiplied current kI.sub.E on the basis of the current provided by the dummy circuit, an amplifier is installed for providing a current ki which corresponds to a multiplication of the current i by an amplification factor of the input circuit, and a second current multiplifier is installed for providing another multiplied current kli which is a multiplication of the current ki by l.