Abstract: A display device includes a first display region and a second display region having a lower pixel density than the first display region. A first pixel circuit in the first display region includes a first drive transistor, a first storage capacitor that stores a control voltage of the first drive transistor, and a first switch transistor that writes a data signal to the first storage capacitor. A second pixel circuit in the second display region includes a second drive transistor, a second storage capacitor that stores a control voltage of the second drive transistor, and a second switch transistor that writes a data signal to the second storage capacitor. A channel width of the second drive transistor is greater than a channel width of the first drive transistor. A channel width of the second switch transistor is greater than a channel width of the first switch transistor.

Abstract: A display device determines a gray level for a first pixel based on video data, determines whether the first pixel is in a first deterioration mode or a second deterioration mode following the first deterioration mode based on a driving history of the first pixel, determines a data signal to be supplied to the first pixel based on the gray level and the driving history of the first pixel with reference to first adjustment information for the first deterioration mode in a case of determining that the first pixel is in the first deterioration mode, and determines a data signal to be supplied to the first pixel based on the gray level and the driving history of the first pixel with reference to second adjustment information for the second deterioration mode in a case of determining that the first pixel is in the second deterioration mode.

Abstract: A display device includes a deterioration evaluation region including dummy pixels and a display region. A control circuit determines a gray level for a first display pixel and determines whether the first display pixel is in a first deterioration mode or a second deterioration mode based on a driving history of the first display pixel. The control circuit determines, in the first deterioration mode, a data signal to be supplied to the first display pixel based on the gray level and the driving history of the first display pixel. The control circuit determines, in the second deterioration mode, a data signal to be supplied to the first display pixel based on the gray level, the driving history of the first display pixel, and measurement results about a current-voltage characteristic acquired from dummy pixels in the deterioration evaluation region of the same color as the first display pixel.

Abstract: A display device includes a display region including display pixels, dummy pixels disposed outside the display region, light blocking films covering the dummy pixels. The display region includes a first region and a second region having a lower display pixel density than the first region. A control circuit is configured to supply the display pixels in the second region with driving current higher than driving current for the first region for the same grayscale level specified in image data, supply each of the dummy pixels with the same data signal as a data signal for the associated display pixel in the second region, measure deterioration of the light-emitting element of each of the dummy pixels, and adjust data signals for the display pixels in the second region associated with the dummy pixels based on results of the measurement.

Abstract: A display panel includes pixels disposed in a delta-nabla layout. Each data line set consists of three data lines of a data line for a first color, a data line for a second color, and a data line for a third color disposed consecutively. An additional data line for the first color is disposed outside the data line sets. Each pixel circuit for the first color in each of pixel circuit column pairs is supplied with a data signal from a data line for the first color closer to the pixel circuit between the data line for the first color in the associated data line set and the data line for the first color located adjacent to the data line for the third color in the associated data line set outside the associated data line set.

Abstract: For the first type of display pixel, a display device determines a luminance value assigned from a first frame pixel to the green subpixel, a luminance value assigned from the first frame pixel to each of the two red subpixels to be a value lower than a luminance value for one red subpixel, and a luminance value assigned from the first frame pixel to each of the two blue subpixels to be a value lower than a luminance value for one blue subpixel. For the second type of display pixel, the display device determines a luminance value assigned from a second frame pixel to each of the red subpixel and the blue subpixel, and a luminance value assigned from the second frame pixel to each of the two green subpixels to be a value lower than a luminance value determined for one green subpixel.

Abstract: A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

Abstract: A display panel includes pixels disposed in a delta-nabla layout. Each data line set consists of three data lines of a data line for a first color, a data line for a second color, and a data line for a third color disposed consecutively. An additional data line for the first color is disposed outside the data line sets. Each pixel circuit for the first color in each of pixel circuit column pairs is supplied with a data signal from a data line for the first color closer to the pixel circuit between the data line for the first color in the associated data line set and the data line for the first color located adjacent to the data line for the third color in the associated data line set outside the associated data line set.

Abstract: A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

Abstract: A display device includes a display region including pixel circuits, and a driver for outputting a control signal to the pixel circuits. The display region includes a first region and a second region having a lower pixel circuit density than the first region. The driver includes output buffers. Each of the output buffers simultaneously outputs the control signal to the pixel circuits. The output buffers include a first output buffer and a second output buffer. The number of the pixel circuits as output destinations of the control signal of the first output buffer is larger than the number of the pixel circuits as output destinations of the control signal of the second output buffer. A channel width of a drive transistor of the first output buffer is larger than that of a drive transistor of the second output buffer.

Abstract: A light-emission control switch transistor and a threshold compensation switch transistor are transistors having different conductivity types. Gate potentials at the light-emission control switch transistor and the threshold compensation switch transistor are controlled using a first control signal. A gate potential at the data signal switch transistor is controlled using a second control signal. A control circuit selects rows sequentially. in a selected one of the rows, the light-emission control switch transistor is maintained off, the threshold compensation switch transistor is maintained on, and the data signal switch transistor is maintained off in a first period. In the selected row, the light-emission control switch transistor is maintained on, the threshold compensation switch transistor is maintained off, and the data signal switch transistor is maintained on in a second period after the first period.

Abstract: A second display region has a lower pixel density than a first display region. A third metal layer is located upper than a first metal layer and a second metal layer. The occupancy of the third metal layer in the second display region is lower than the occupancy in the first display region. In a pixel unit, the first metal layer includes a first electrode region to control an amount of electric current in a driving transistor, the second metal layer includes a second electrode region and a third electrode region to supply current to the driving transistor, and the third metal layer includes a main region to form a capacitor included in a capacitive element to store a control voltage for the driving transistor, and an island region surrounded by the main region with a gap and interconnected with a lower electrode region by a via region.

Abstract: A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

Abstract: A display device includes a first polyimide layer, a first silicon oxide layer located above and in direct contact with the first polyimide layer, an amorphous silicon layer located above and in direct contact with the first silicon oxide layer, a second polyimide layer located above and in direct contact with the amorphous silicon layer, a plurality of light-emitting elements located above the second polyimide layer, a transistor array located above the second polyimide layer, the transistor array being configured to control light emission of the plurality of light-emitting elements, a transparent conductive layer located between the transistor array and the second polyimide layer, and a second silicon oxide layer located between and in direct contact with the transparent conductive layer and the second polyimide layer.

Abstract: A display device includes a display panel and a control circuit configured to process a signal for the display panel. The control circuit is configured to acquire respective gray levels specifying brightness for a plurality of subpixels in one subpixel row, determine correction amounts to the gray levels for the plurality of subpixels based on distribution of the gray levels and the individual gray levels for the plurality of subpixels, and correct the gray levels for the plurality of subpixels by the correction amounts.

Abstract: A driver is configured to maintain a threshold compensation transistor to be ON to write a threshold compensation voltage to a storage capacitor in a threshold compensation period, and write a data signal to the storage capacitor in a data write period after the threshold compensation period. A pulse width of control signal is twice or more as long as the data write period. The driver circuit is configured to turn ON a first transistor with a start edge of a first control signal pulse before the data write period starts, maintain the first transistor to be ON and turn ON a second transistor with a start edge of a second control signal pulse to start the data write period, and turn OFF the first transistor with an end edge of the first control signal pulse to end the data write period.

Abstract: A display device includes a display region including pixel circuits, and a driver for outputting a control signal to the pixel circuits. The display region includes a first region and a second region having a lower pixel circuit density than the first region. The driver includes output buffers. Each of the output buffers simultaneously outputs the control signal to the pixel circuits. The output buffers include a first output buffer and a second output buffer. The number of the pixel circuits as output destinations of the control signal of the first output buffer is larger than the number of the pixel circuits as output destinations of the control signal of the second output buffer. A channel width of a drive transistor of the first output buffer is larger than that of a drive transistor of the second output buffer.

Abstract: A driver is configured to maintain a threshold compensation transistor to be ON to write a threshold compensation voltage to a storage capacitor in a threshold compensation period, and write a data signal to the storage capacitor in a data write period after the threshold compensation period. A pulse width of control signal is twice or more as long as the data write period. The driver circuit is configured to turn ON a first transistor with a start edge of a first control signal pulse before the data write period starts, maintain the first transistor to be ON and turn ON a second transistor with a start edge of a second control signal pulse to start the data write period, and turn OFF the first transistor with an end edge of the first control signal pulse to end the data write period.

Abstract: A display device includes a first display region and a second display region having a lower pixel density than the first display region. A first pixel circuit in the first display region includes a first drive transistor, a first storage capacitor that stores a control voltage of the first drive transistor, and a first switch transistor that writes a data signal to the first storage capacitor. A second pixel circuit in the second display region includes a second drive transistor, a second storage capacitor that stores a control voltage of the second drive transistor, and a second switch transistor that writes a data signal to the second storage capacitor. A channel width of the second drive transistor is greater than a channel width of the first drive transistor. A channel width of the second switch transistor is greater than a channel width of the first switch transistor.

Abstract: A light-emission control switch transistor and a threshold compensation switch transistor are transistors having different conductivity types. Gate potentials at the light-emission control switch transistor and the threshold compensation switch transistor are controlled using a first control signal. A gate potential at the data signal switch transistor is controlled using a second control signal. A control circuit selects rows sequentially. in a selected one of the rows, the light-emission control switch transistor is maintained off, the threshold compensation switch transistor is maintained on, and the data signal switch transistor is maintained off in a first period. In the selected row, the light-emission control switch transistor is maintained on, the threshold compensation switch transistor is maintained off, and the data signal switch transistor is maintained on in a second period after the first period.