Patents by Inventor Yokichi Itoh
Yokichi Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5519244Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: July 6, 1994Date of Patent: May 21, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5348898Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 26, 1993Date of Patent: September 20, 1994Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5252505Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 15, 1992Date of Patent: October 12, 1993Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5114870Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: May 15, 1989Date of Patent: May 19, 1992Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 4851364Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: April 10, 1986Date of Patent: July 25, 1989Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 4654828Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.Type: GrantFiled: October 15, 1985Date of Patent: March 31, 1987Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Yokichi Itoh, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami
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Patent number: 4586238Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: April 21, 1983Date of Patent: May 6, 1986Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 4460980Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.Type: GrantFiled: October 2, 1980Date of Patent: July 17, 1984Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Yokichi Itoh, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami
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Patent number: 4429326Abstract: An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.Type: GrantFiled: November 21, 1979Date of Patent: January 31, 1984Assignee: Hitachi, Ltd.Inventors: Tomoyuki Watanabe, Kenji Kaneko, Tohru Nakamura, Yutaka Okada, Takahiro Okabe, Minoru Nagata, Yokichi Itoh, Toru Toyabe
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Patent number: 4264376Abstract: A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.Type: GrantFiled: August 15, 1979Date of Patent: April 28, 1981Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Shinichi Minami, Ryuji Kondo, Takaaki Hagiwara, Yokichi Itoh
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Patent number: 4041521Abstract: A shift array for shifting carriers introduced into a semiconductor body toward the X-direction and Y-direction comprises an insulating layer disposed on the semiconductor body, first electrodes disposed on the insulating layer and arranged in a matrix on the X-Y plane, second electrodes disposed between adjacent first electrodes, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each row when carriers are transferred toward the Y-direction, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each column when carriers are transferred toward the X-direction. When carriers are transferred toward the X-direction, the second electrodes disposed between the adjacent first electrodes of each column are biased with a DC voltage whose electrical polarity is reversed relative to the DC voltage applied to the first electrodes for preventing the transit of carriers toward the Y-direction.Type: GrantFiled: October 18, 1972Date of Patent: August 9, 1977Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Yokichi Itoh, Fumiyuki Inose, Yoshiaki Kamigaki
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Patent number: 4013897Abstract: A charge transfer device and method are disclosed in which a plurality of signal charges corresponding to one information input signal are injected into a surface region of a semiconductor substrate beneath specific ones of a plurality of transfer gate electrodes corresponding to said signal charges and transferred therethrough by the transfer gate electrodes. Transferred signal charges subsequent to the first signal charge transferred are detected, thereby using residual charges to prevent decrease in the amount of the detected transfer charges and thus allowing the output signal to appear at the output terminal with a minimum of attenuation even if an increased number of transfer gate electrodes are used.Type: GrantFiled: November 1, 1974Date of Patent: March 22, 1977Assignee: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Hideo Sunami, Yokichi Itoh