Abstract: To provide a PMOS transistor that is arranged within an N-well formed in a P-type semiconductor substrate and that is connected to an external terminal; and an MOS gate capacitor that is positioned adjacent to the PMOS transistor and of which one end and the other end are supplied with a power supply potential and a ground potential, respectively. An N-type diffusion layer that becomes a cathode of a PNPN parasitic thyristor configured by the PMOS transistor and the MOS gate capacitor is fixed to the power supply potential. This structure does not permit turning on of the PNPN parasitic thyristor, and thus a problem that a device is broken by a latch-up phenomenon is eliminated.

Abstract: Semiconductor Integrated Circuit (IC) devices such as diode and MOSFET that protect circuits from Electrostatic Discharge (ESD) are formed. A diode is formed by an N+ (or P+) and P+ (or N+) diffusion layers within an N (or P) well on a P (or N) type semiconductor substrate. The N+ (or P+) diffusion layer of the diode is connected to the power supply. Additionally, an NMOSFET (or PMOSFET) is formed with N+ (or P+) source/drain regions and a gate on the same P (or N) type substrate. The P+ (or N+) diffusion layer of the diode and the N+ (or P+) source/drain regions of the NMOSFET (or PMOSFET) are connected to a fuse through second and first levels of metal wirings.

Abstract: A diode is formed by an N+ diffusion layer and a P-type semiconductor substrate. In an N-well, a diode is formed by a P+ diffusion layer and an N+ diffusion layer. The N+ diffusion layer is connected to power supply wiring. A fuse is connected to the N+ diffusion layer and the P+ diffusion layer.

Abstract: A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.

Abstract: A semiconductor device having resistance to static electricity damage under the CDM is disclosed. The semiconductor device may include a plurality of input/output terminals (102), a first reference electric potential connection (101) electrically connected to the terminals, an input/output protection element (103) electrically connected between the terminals and the first reference electric potential connection (101). A board electric potential generator (104) may provide a potential to a board electric potential connection. A clamp element (105) may be electrically connected between the first reference electric potential and the board electric potential connection.

Abstract: A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.

Abstract: A semiconductor device having resistance to static electricity damage under the CDM is disclosed. The semiconductor device may include a plurality of input/output terminals (102), a first reference electric potential connection (101) electrically connected to the terminals, an input/output protection element (103) electrically connected between the terminals and the first reference electric potential connection (101). A board electric potential generator (104) may provide a potential to a board electric potential connection. A clamp element (105) may be electrically connected between the first reference electric potential and the board electric potential connection.