Abstract: A semiconductor device includes a semiconductor body including first to fourth semiconductor layers. The second semiconductor layer of second conductivity type is provided on the first semiconductor layer of first conductivity type; the third semiconductor layer of first conductivity type is provided selectively on the second semiconductor layer; and the fourth semiconductor layer of second conductivity type is provided selectively on the second semiconductor layer. The semiconductor device further includes first and second control electrodes. The first and second control electrodes are provided inside the semiconductor body and oppose the second semiconductor layer with first and second insulating films interposed, respectively, and are arranged alternately with a third insulating layer interposed. The first control electrode contacts the third insulating layer at a first surface thereof, and the second control electrode contacts the third insulating layer at a second surface opposite to the first surface.

Abstract: A semiconductor device includes a semiconductor layer having a first plane and a second plane; an emitter electrode on a side of the first plane; at least one collector electrode on a side of the second plane; a first gate electrode on the side of the first plane; at least one second gate electrode on the side of the second plane; a drift region of a first conductivity-type in the semiconductor layer; a collector region of a second conductivity-type in the semiconductor layer; and a first conductivity-type region of the first conductivity-type provided between a part of the collector region and the second plane, wherein the semiconductor device has a first effective gate distance and a second effective gate distance different from the first effective gate distance.

Abstract: A semiconductor device includes a semiconductor body; a first electrode on the semiconductor body; control electrodes provided in the semiconductor body along the surface thereof; and first films electrically insulating the control electrodes from the semiconductor body. The semiconductor body includes first, third, sixth layers of a first conductivity type, and second, fourth, fifth layers of a second conductivity type. The second to sixth layers are provided between the first electrode and the first layer. The second and third layers are positioned between two adjacent control electrodes. The fourth to sixth layers are positioned between other two adjacent control electrodes. The sixth layer positioned between the fourth layer and the fifth layer. The sixth layer includes a major portion and a boundary portion between the major portion and one of the first films. An impurity concentration in the boundary portion is lower than that in the major portion.

Abstract: A semiconductor circuit of an embodiment includes semiconductor device and a control circuit. The semiconductor device includes a semiconductor layer that has a first region of a first-conductivity type, a second region of a second-conductivity type, a third region of the first-conductivity type, fourth region of the second-conductivity type, first and second trench, first and second gate electrode, a first gate insulating film in contact with the fourth region, and a second gate insulating film spaced away from the fourth region. The semiconductor device includes a first gate electrode pad connected to the first gate electrode, and a second gate electrode pad connected to the second gate electrode. Prior to changing a first gate voltage from a turn-ON voltage to a turn-OFF voltage, a second gate voltage changed from a first voltage to a second voltage. The second voltage is a negative voltage when the first-conductivity type is p-type.

Abstract: A semiconductor device according to as embodiment includes a semiconductor layer having a first plane and a second plane; a first trench provided in the semiconductor layer; a first gate electrode provided in the first trench; a second trench provided in the semiconductor layer; a second gate electrode provided in the second trench; a third trench provided in the semiconductor layer; a first resistive layer provided in the third trench; a first electrode provided on a side of the first plane of the semiconductor layer; a second electrode provided on a side of the second plane of the semi conductor layer; and a gate electrode pad provided on the side of the first plane of the semiconductor layer, is electrically connected to the first gate electrode through the first resistive layer, and is electrically connected to the second gate electrode.

Abstract: A semiconductor device according to as embodiment includes a semiconductor layer having a first plane and a second plane; a first trench provided in the semiconductor layer; a first gate electrode provided in the first trench; a second trench provided in the semiconductor layer; a second gate electrode provided in the second trench; a third trench provided in the semiconductor layer; a first resistive layer provided in the third trench; a first electrode provided on a side of the first plane of the semiconductor layer; a second electrode provided on a side of the second plane of the semi conductor layer; and a gate electrode pad provided on the side of the first plane of the semiconductor layer, is electrically connected to the first gate electrode through the first resistive layer, and is electrically connected to the second gate electrode.

Abstract: A semiconductor device according to an embodiment includes a transistor including a first electrode, a second electrode, and a first gate electrode; a first detector detecting a change in a first parameter of the transistor over time to acquire first temporal change data; and a first storage storing the first temporal change data.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first insulating layer that has refractive index of 1.95 or less, contains silicon nitride, and located on the semiconductor layer, and a resin that is provided on the first insulating layer and is in contact with the first insulating layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.

Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.

Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

Abstract: According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.

Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.

Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a resistance change portion and a select element. The resistance change portion is provided between the first electrode and the second electrode and configured to transition between a first resistance state and a second resistance state. The select element is provided between the resistance change portion and the first electrode and has a p-layer including a p-type semiconductor, an i-layer including an intrinsic semiconductor, and an n-layer including an n-type semiconductor. The select element contains an impurity having a smaller bandgap energy than the intrinsic semiconductor, and a concentration peak of the impurity in the i-layer is placed in a center portion of layer thickness of the i-layer.

Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.