Patents by Inventor Yoko Masuo

Yoko Masuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12197724
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The nonvolatile memory includes physical blocks. The controller is configured to assign each of a plurality of block groups, each block group including a predetermined number or more of the physical blocks, to one of categories. The controller assigns block groups having a total capacity equal to a fraction of the overprovisioning capacity that is equal to a first threshold value, to the first category, and block groups having a total capacity equal to a remaining part of the overprovisioning capacity to the third category. When an overprovisioning ratio falls below a second threshold value, the controller reassigns one or more block groups in the third category to the first category.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventors: Hiromi Hoshino, Yoko Masuo
  • Patent number: 12086429
    Abstract: According to one embodiment, the controller periodically executes a first operation. The controller selects a first mode or a second mode in the first operation. In a case where the first mode is selected, the controller reads pieces of data that are stored in contiguous memory locations, respectively, that are included in a first physical page or a second physical page. The first physical page is included in a first physical block of a first die. The second physical page is included in a second physical block of a second die. In a case where the second mode is selected, the controller reads first data stored in one memory location of the first physical page and second data stored in one memory location of the second physical page.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: September 10, 2024
    Assignee: Kioxia Corporation
    Inventor: Yoko Masuo
  • Publication number: 20240069723
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The nonvolatile memory includes physical blocks. The controller is configured to assign each of a plurality of block groups, each block group including a predetermined number or more of the physical blocks, to one of categories. The controller assigns block groups having a total capacity equal to a fraction of the overprovisioning capacity that is equal to a first threshold value, to the first category, and block groups having a total capacity equal to a remaining part of the overprovisioning capacity to the third category. When an overprovisioning ratio falls below a second threshold value, the controller reassigns one or more block groups in the third category to the first category.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 29, 2024
    Inventors: Hiromi HOSHINO, Yoko MASUO
  • Patent number: 11853204
    Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoko Masuo, Yosuke Mitsumasu
  • Publication number: 20230376223
    Abstract: According to one embodiment, the controller periodically executes a first operation. The controller selects a first mode or a second mode in the first operation. In a case where the first mode is selected, the controller reads pieces of data that are stored in contiguous memory locations, respectively, that are included in a first physical page or a second physical page. The first physical page is included in a first physical block of a first die. The second physical page is included in a second physical block of a second die. In a case where the second mode is selected, the controller reads first data stored in one memory location of the first physical page and second data stored in one memory location of the second physical page.
    Type: Application
    Filed: March 13, 2023
    Publication date: November 23, 2023
    Inventor: Yoko MASUO
  • Publication number: 20230103470
    Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Applicant: Kioxia Corporation
    Inventors: Yoko MASUO, Yosuke MITSUMASU
  • Publication number: 20230070976
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks. The controller controls the nonvolatile memory. The controller acquires a write amount to the nonvolatile memory in a first period. The controller calculates an estimated amount of writing to the nonvolatile memory in the first period. The controller changes, when the write amount is larger than the estimated amount by a first threshold value or more, one or more parameters used for writing of data to the nonvolatile memory.
    Type: Application
    Filed: November 11, 2022
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventor: Yoko MASUO
  • Publication number: 20220405008
    Abstract: According to one embodiment, a memory system includes a nonvolatile, memory and a controller. The nonvolatile memory includes a first block, a second block and a third block. In a first case where the first block is a block being allocated to the first area, and the second block is a block storing no valid data, the controller selects the second block as a block to which the data that has to be refreshed is to be moved. In a second case where the first block is a block being allocated to the second area, and the third block is a block in which valid data of a block different from the first block is possibly to be mixed, the controller selects the third block as a block to which the data that has to be refreshed is to be moved.
    Type: Application
    Filed: December 13, 2021
    Publication date: December 22, 2022
    Inventor: Yoko MASUO
  • Patent number: 11526436
    Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 13, 2022
    Assignee: Kioxia Corporation
    Inventors: Yoko Masuo, Yosuke Mitsumasu
  • Patent number: 11500584
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks. The controller controls the nonvolatile memory. The controller acquires a write amount to the nonvolatile memory in a first period. The controller calculates an estimated amount of writing to the nonvolatile memory in the first period. The controller changes, when the write amount is larger than the estimated amount by a first threshold value or more, one or more parameters used for writing of data to the nonvolatile memory.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventor: Yoko Masuo
  • Patent number: 11182287
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 23, 2021
    Assignee: Kioxia Corporation
    Inventors: Yoko Masuo, Yosuke Mitsumasu, Kazuya Kitsunai
  • Publication number: 20210240392
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks. The controller controls the nonvolatile memory. The controller acquires a write amount to the nonvolatile memory in a first period. The controller calculates an estimated amount of writing to the nonvolatile memory in the first period. The controller changes, when the write amount is larger than the estimated amount by a first threshold value or more, one or more parameters used for writing of data to the nonvolatile memory.
    Type: Application
    Filed: September 8, 2020
    Publication date: August 5, 2021
    Applicant: Kioxia Corporation
    Inventor: Yoko MASUO
  • Publication number: 20210117317
    Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.
    Type: Application
    Filed: July 24, 2020
    Publication date: April 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Yoko MASUO, Yosuke MITSUMASU
  • Publication number: 20210073118
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.
    Type: Application
    Filed: February 11, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Yoko MASUO, Yosuke MITSUMASU, Kazuya KITSUNAI
  • Patent number: 9384124
    Abstract: According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taichiro Yamanaka, Yoko Masuo, Hironobu Miyamoto
  • Patent number: 9361201
    Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoko Masuo, Hironobu Miyamoto
  • Patent number: 9323661
    Abstract: A memory system has a storage unit having two or more parallel read/write processing elements and non-volatile data recording areas for a logical block divided into a plurality of logical pages, and a control unit that generates log information for each unit of data written into the recording areas, determines for each logical page a log information recording area from a group of recording areas of the logical page, and controls the parallel operation elements to write the log information generated for a logical page into the log information recording area of the logical page and the data of the logical page into the other recording areas of the group of recording areas of the logical page.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akinori Harasawa, Yoko Masuo
  • Patent number: 9189313
    Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Motohiro Matsuyama, Yoko Masuo, Gen Ohshima
  • Patent number: 8930614
    Abstract: According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Masuo, Yoshimasa Aoyama, Hironobu Miyamoto
  • Publication number: 20140317651
    Abstract: According to one embodiment, the purpose of this invention is to provide an electronic device which can output information in accordance with a schedule of each person. The electronic device of the embodiments has a manager, an identifier, and a controller. The manager manages a schedule corresponding to personal identification information. The identifier identifies the personal identification information from input information. The controller controls output of schedule-related information regarding the schedule corresponding to the identified personal identification information and output of content.
    Type: Application
    Filed: September 23, 2013
    Publication date: October 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoko Masuo, Shunji Ui, Takanori Yamaguchi