Abstract: A yield of a device including a plurality of memory circuits is calculated. In the calculation, in the case where at least two or more memory circuits out of the plural memory circuits share a fuse used for redundancy repair, the two or more memory circuits sharing the fuse are replaced with one memory circuit having a capacity equal to the total capacity of the two or more memory circuits for calculating the yield of the device.

Abstract: An effective critical area value of each circuit element of a target product is obtained on the basis of an effective critical area value per unit area or per unit capacity of each circuit element previously calculated and the area or capacity of each circuit element of the target product. The yield of the target product is calculated by using the effective critical area value of each circuit element of the target product, a defect density to be obtained on a fabrication line for the target product and a given yield model.

Abstract: An evaluation semiconductor device is used for evaluating a yield of a DRAM portion of an integrated circuit device. The evaluation semiconductor device includes an evaluation gate interconnect provided in a layer corresponding to a gate interconnect layer of the DRAM portion; and an evaluation source contact corresponding to a source contact of a capacitor included in the DRAM portion and connected to the evaluation gate interconnect.

Abstract: A critical area of one via is calculated on the basis of sizes of a plurality of vias, sizes of defects causing random defect failures of the plural vias and a distance from the one via to another adjacent via.

Abstract: A pattern analysis method includes: a first step of preparing pattern layout data including a plurality of first regions and a plurality of second regions; a second step of selecting either said plurality of first regions or said plurality of second regions as a target region in which a critical area of said pattern layout data is to be calculated; and a third step of extracting, from said target region, rectangular regions each having a width within a given range. The method further includes; a fourth step of obtaining a total area of said rectangular regions; and a fifth step of calculating said critical area by using said total area.

Abstract: A product of a probability that failure-related defects in the number larger than the number of redundancy repairs occur in one layer included in a memory cell array and a probability that no failure-related defect occurs in the other layers of the memory cell array is used for calculating a yield.