Patents by Inventor Yon-sup Pang
Yon-sup Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387104Abstract: A semiconductor device including: a semiconductor substrate including a buried layer; and a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate, wherein the deep trench isolation includes: a first point disposed near the upper surface of the semiconductor substrate; a second point disposed near the buried layer; and a third point disposed near a bottom face of the deep trench isolation, and wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point, is disclosed.Type: ApplicationFiled: October 13, 2022Publication date: November 30, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Yon Sup PANG, Young Ju KIM
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Publication number: 20230369391Abstract: A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: KEY FOUNDRY CO., LTD.Inventor: Yon Sup PANG
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Patent number: 11756992Abstract: A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.Type: GrantFiled: August 29, 2022Date of Patent: September 12, 2023Assignee: KEY FOUNDRY CO., LTD.Inventor: Yon Sup Pang
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Patent number: 10923603Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.Type: GrantFiled: December 4, 2019Date of Patent: February 16, 2021Assignee: Key Foundry Co., Ltd.Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
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Publication number: 20200105947Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Yon Sup PANG, Hyun Kwang SHIN, Tae Hoon LEE
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Patent number: 10586863Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: GrantFiled: May 22, 2017Date of Patent: March 10, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
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Patent number: 10566465Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.Type: GrantFiled: May 30, 2018Date of Patent: February 18, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
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Publication number: 20190103498Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.Type: ApplicationFiled: May 30, 2018Publication date: April 4, 2019Applicant: Magnachip Semiconductor, Ltd.Inventors: Yon Sup PANG, Hyun Kwang SHIN, Tae Hoon LEE
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Publication number: 20170263762Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: ApplicationFiled: May 22, 2017Publication date: September 14, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Francois HEBERT, Yon Sup PANG, Yu Shin RYU, Seong Min CHO, Ju Ho KIM
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Patent number: 9705010Abstract: The present examples relate to a Schottky diode having floating guard rings and an additional element isolation layer configured to further improve a breakdown voltage of the Schottky diode, while maintaining the turn-on voltage and current in the forward characteristic, compared to a related Schottky diode. The floating guard rings in the examples are located in a position between the anode and the cathode regions or under the anode.Type: GrantFiled: December 14, 2015Date of Patent: July 11, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Yon Sup Pang, Hyun Chul Kim
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Patent number: 9691893Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: GrantFiled: October 20, 2014Date of Patent: June 27, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
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Patent number: 9666700Abstract: The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.Type: GrantFiled: October 28, 2014Date of Patent: May 30, 2017Assignee: MagnaChip Semiconductor, Ltd.Inventors: Francois Hebert, Yon Sup Pang, Seong Min Cho, Ju Ho Kim
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Publication number: 20160343881Abstract: The present examples relate to a Schottky diode having floating guard rings and an additional element isolation layer configured to further improve a breakdown voltage of the Schottky diode, while maintaining the turn-on voltage and current in the forward characteristic, compared to a related Schottky diode. The floating guard rings in the examples are located in a position between the anode and the cathode regions or under the anode.Type: ApplicationFiled: December 14, 2015Publication date: November 24, 2016Applicant: Magnachip Semiconductor, Ltd.Inventors: Yon Sup PANG, Hyun Chul KIM
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Publication number: 20150255595Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: ApplicationFiled: October 20, 2014Publication date: September 10, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Francois HEBERT, Yon Sup PANG, Yu Shin RYU, Seong Min CHO, Ju Ho KIM
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Publication number: 20150243770Abstract: The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.Type: ApplicationFiled: October 28, 2014Publication date: August 27, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Francois HEBERT, Yon Sup PANG, Seong Min CHO, Ju Ho KIM
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Patent number: 9111959Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well region disposed in a substrate, a gate disposed on the substrate, a halo region disposed in a channel region under the gate, and a source LDD region and a drain LDD region disposed on opposite sides of the halo region.Type: GrantFiled: December 20, 2013Date of Patent: August 18, 2015Assignee: MagnaChip Semiconductor, Ltd.Inventor: Yon Sup Pang
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Patent number: 9105721Abstract: A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region.Type: GrantFiled: March 17, 2014Date of Patent: August 11, 2015Assignee: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Yon-sup Pang, Jun-ho Lee
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Publication number: 20140367776Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well region disposed in a substrate, a gate disposed on the substrate, a halo region disposed in a channel region under the gate, and a source LDD region and a drain LDD region disposed on opposite sides of the halo region.Type: ApplicationFiled: December 20, 2013Publication date: December 18, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventor: Yon Sup PANG
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Publication number: 20140231927Abstract: A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region.Type: ApplicationFiled: March 17, 2014Publication date: August 21, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Yon-sup Pang, Jun-ho Lee
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Patent number: 8674442Abstract: A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region.Type: GrantFiled: November 16, 2010Date of Patent: March 18, 2014Assignee: Magnachip Semiconductor, Ltd.Inventors: Yon-sup Pang, Jun-ho Lee