Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Abstract: Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.

Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.

Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Abstract: Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.

Abstract: A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.

Abstract: Methods for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment converts interstitial carbon to substitutional carbon in the epitaxial layer, according to one or more embodiments. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the treatment of the epitaxial layer involves annealing for short periods of time, for example, by laser annealing, millisecond annealing, rapid thermal annealing, spike annealing and combinations thereof. Embodiments include amorphization of at least a portion of the epitaxial layer containing silicon and carbon.

Abstract: A method for forming an ultra shallow junction on a substrate is provided. In certain embodiments a method of forming an ultra shallow junction on a substrate is provided. The substrate is placed into a process chamber. A silicon carbon layer is deposited on the substrate. The silicon carbon layer is exposed to a dopant. The substrate is heated to a temperature greater than 950° C. so as to cause substantial annealing of the dopant within the silicon carbon layer. In certain embodiments the substrate is heated to a temperature between about 1000° C. and about 1100°. In certain embodiments the substrate is heated to a temperature between about 1030° C. and 1050° C. In certain embodiments, a structure having an abrupt p-n junction is provided.

Abstract: Methods for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment converts interstitial carbon to substitutional carbon in the epitaxial layer, according to one or more embodiments. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the treatment of the epitaxial layer involves annealing for short periods of time, for example, by laser annealing, millisecond annealing, rapid thermal annealing, spike annealing and combinations thereof. Embodiments include amorphization of the epitaxial layer containing silicon and carbon.

Abstract: Methods for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment converts interstitial carbon to substitutional carbon in the epitaxial layer, according to one or more embodiments. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the treatment of the epitaxial layer involves annealing for short periods of time, for example, by laser annealing, millisecond annealing, rapid thermal annealing, spike annealing and combinations thereof. Embodiments include amorphization of at least a portion of the epitaxial layer containing silicon and carbon.

Abstract: A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner.

Abstract: A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.

Abstract: A method for forming an ultra shallow junction on a substrate is provided. In certain embodiments a method of forming an ultra shallow junction on a substrate is provided. The substrate is placed into a process chamber. A silicon carbon layer is deposited on the substrate. The silicon carbon layer is exposed to a dopant. The substrate is heated to a temperature greater than 950° C. so as to cause substantial annealing of the dopant within the silicon carbon layer. In certain embodiments the substrate is heated to a temperature between about 1000° C. and about 1100°. In certain embodiments the substrate is heated to a temperature between about 1030° C. and 1050° C. In certain embodiments, a structure having an abrupt p-n junction is provided.

Abstract: A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.