Abstract: Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to online activation compression with K-means are described. In one embodiment, logic (e.g., in a processor) compresses one or more activation functions for a convolutional network based on non-uniform quantization. The non-uniform quantization for each layer of the convolutional network is performed offline, and an activation function for a specific layer of the convolutional network is quantized during runtime. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for incremental network quantization. In an example, an apparatus comprises logic, at least partially comprising hardware logic to determine a plurality of weights for a layer of a convolutional neural network (CNN) comprising a plurality of kernels; organize the plurality of weights into a plurality of clusters for the plurality of kernels; and apply a K-means compression algorithm to each of the plurality of clusters. Other embodiments are also disclosed and claimed.

Abstract: A processor includes a linear approximator and a front end including circuitry to assign linear approximation of a nonlinear function to a linear approximator. The linear approximator includes circuitry to divide a range of values for the linear approximation into a defined number of segments, perform linear approximation for each segment, move borders between the segments to reduce discontinuity moving along segments of variable length, repeat linear approximation for each segment until convergence, and return values for the linear approximation.

Abstract: A processor includes a linear approximator and a front end including circuitry to assign linear approximation of a nonlinear function to a linear approximator. The linear approximator includes circuitry to divide a range of values for the linear approximation into a defined number of segments, perform linear approximation for each segment, move borders between the segments to reduce discontinuity moving along segments of variable length, repeat linear approximation for each segment until convergence, and return values for the linear approximation.