Patents by Inventor Yonatan Meir Levitt

Yonatan Meir Levitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips
    Patent number: 11949595
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta
  • REFLECTION ROUTING AS A FRAMEWORK FOR ADAPTIVE MODULAR LOAD BALANCING FOR MULTI-HIERARCHY NETWORK ON CHIPS
    Publication number: 20200336424
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta