Abstract: An apparatus for automatically inspecting the welding state of a battery module is configured to inspect welding states of welding parts of a plurality of leads for electrical connection based on a deep penetration inspection using application of eddy current to the welding parts of the leads.

Abstract: An apparatus of storing container includes a stocker including shelves being configured to support containers, respectively, a purging unit being configured to provide a purge gas for each of the shelves to purge the containers when the stocker is in a purge mode, and to provide the purge gas only for each of the shelves when the stocker is in a normal mode, an inspection unit being configured to inspect a purge quality of the purge gas provided to each of the shelves while the stocker is in the normal mode, and a control unit being configured to change the stocker between in the purge mode and in the normal mode, and being configured to control the purging unit according to a switch between the purge mode and the normal mode. Thus, the apparatus has improved operation efficiency.

Abstract: An article storage device includes a load port configured to load and unload a plurality of articles, a plurality of shelves configured to load the articles, a transportation robot configured to transport the articles between the load port and the shelves or between the shelves, a receiving part configured to receive operation commands of the transportation robot from an upper system, a calculating part configured to calculate a setting value of an order of priority with respect to the operation commands, and a control part configured to control the transportation robot to perform an operation command having a high setting value of an order of priority among the operation commands.

Abstract: A radio frequency (RF) power amplifier comprises an output stage amplifying circuit and a counterpart waveform generator. The output stage amplifying circuit receives a first waveform through an input node and amplifies the first waveform so as to output an amplified waveform through an output node. The counterpart waveform generator generates a second waveform corresponding to a portion of frequency components of the first waveform. The output stage amplifying circuit and the counterpart waveform generator are electrically coupled such that the second waveform is applied to the input node of the output stage amplifying circuit to substantially compensate the portion of frequency components of the first waveform.

Abstract: A radio frequency (RF) power amplifier comprises an output stage amplifying circuit and a counterpart waveform generator. The output stage amplifying circuit receives a first waveform through an input node and amplifies the first waveform so as to output an amplified waveform through an output node. The counterpart waveform generator generates a second waveform corresponding to a portion of frequency components of the first waveform. The output stage amplifying circuit and the counterpart waveform generator are electrically coupled such that the second waveform is applied to the input node of the output stage amplifying circuit to substantially compensate the portion of frequency components of the first waveform.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: Integrated circuits include an integrated circuit substrate and a plurality of active regions and isolation regions in the integrated circuit substrate. A plurality of conductive and insulating layers are included on the integrated circuit substrate that define regions of high and low topography on the integrated circuit substrate. An underlying wiring layer is provided on the low topography region, but not on the high topography region. An overlying wiring layer is provided on the low topography region and on the high topography region. An insulating layer is provided between the underlying wiring layer and the overlying wiring layer. Memory integrated circuit, DRAM integrated circuit, MML integrated circuit and MDL integrated circuit embodiments may be provided.

Abstract: A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate insulating layer, a first gate electrode, first lightly doped regions in the well region adjacent opposite sides of the first gate electrode, and first heavily doped regions in the well region adjacent the first lightly doped regions opposite the first gate electrode. The first gate insulating layer is adjacent the first well region and has a first thickness. The first gate electrode is on the first gate insulating layer, and the first lightly doped regions define a first transistor channel therebetween and have a second conductivity type and a first light dopant concentration. The first heavily doped regions have the second conductivity and a first heavy dopant concentration.

Abstract: A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.

Abstract: A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate insulating layer, a first gate electrode, first lightly doped regions in the well region adjacent opposite sides of the first gate electrode, and first heavily doped regions in the well region adjacent the first lightly doped regions opposite the first gate electrode. The first gate insulating layer is adjacent the first well region and has a first thickness. The first gate electrode is on the first gate insulating layer, and the first lightly doped regions define a first transistor channel therebetween and have a second conductivity type and a first light dopant concentration. The first heavily doped regions have the second conductivity and a first heavy dopant concentration.

Abstract: Charges stored in a non-volatile semiconductor memory cell are erased in a manner that reduces leakage current. The cell includes source and drain regions formed on one surface of a semiconductor substrate. A channel region is defined by the source and drain regions. A tunnel oxide layer is formed over the channel region and a floating gate layer is formed on the tunnel oxide layer to store the charges. A control gate layer is formed over the floating gate. A first positive voltage is applied to the source region and a negative voltage is applied to the control gate layer. A second positive voltage is applied to the substrate. The combination of applied voltages reduces leakage current, in turn improving cell operating performance.

Abstract: A highly integrated flash memory device having a stable cell is provided.

Abstract: A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.

Abstract: An electrically programmable fuse element includes a fuse having a first end coupled to a data output node selectively coupled, e.g., via a PMOS pull-up transistor, to a power source voltage, e.g., Vcc or Vpp, and a second end, a bipolar transistor connected between the second end of the fuse and a reference potential (e.g., Vss), a first MOS transistor having a channel connected between the base of the bipolar transistor and the reference potential, and a gate electrode coupled to a fuse program control signal, a second MOS transistor having a channel connected between the second end of the fuse and the reference potential, and a gate electrode coupled to a read-out control signal.