Abstract: A self-moving cleaning robot comprises a body and a water tank. The water tank includes a tank body having an air duct and a fan accommodation cavity extending from the bottom of the tank body toward the top of the tank body. An opening end of the fan accommodation cavity faces downwards of the tank body. An air inlet is provided on a side wall of the tank body, and an air outlet is provided at the top of the fan accommodation cavity. The air duct is formed in an inner cavity of the tank body, comprising a second channel formed by side walls of the fan accommodation cavity and corresponding portions of side walls of the tank body, and a first channel located in the inner cavity of the tank body between the air inlet and the fan accommodation cavity.

Abstract: An illustrative calibration member made from a material that scatters light may be used to perform a calibration operation with respect to an optical measurement device having a plurality of light sources and a plurality of detectors distributed among a plurality of modules. The calibration member may form an exterior surface configured to support the optical measurement device and scatter photons of light emitted by the optical measurement device. The calibration operation may be performed based on arrival times of the scattered photons detected by the optical measurement device.

Abstract: An illustrative optical measurement system may include a module comprising a light source configured to emit light directed at a target, a plurality of detectors configured to detect target photon arrival times of target photons of the light after the light is scattered by the target, and a reference detector configured to detect reference photon arrival times of reference photons of the light after the light is reflected within the module. The system may further include a controller configured to determine, based on an output from the reference detector, an instrument response function (IRF) of the module.

Abstract: Provided is a cleaning apparatus, including a liquid supply tank, a liquid storage tank, a first cleaning component, a first rib, disposed on the first cleaning component, for being in contact with a member to be cleaned; where the first rib has two opposite walls protruding above a top surface of the first cleaning component, and the two opposite walls extend along a length direction of the first cleaning component; and a liquid supply port, supplying cleaning liquid in the liquid supply tank to the first cleaning component, where the liquid supply port faces down toward a liquid input end of the first cleaning component; and where liquid injected from the liquid input end flows toward the member to be cleaned and cleans the member to be cleaned under a guidance of the two opposite walls, and is collected to the liquid storage tank.

Abstract: An illustrative calibration member made from a material that scatters light may be used to perform a calibration operation with respect to an optical measurement device having a plurality of light sources and a plurality of detectors distributed among a plurality of modules. The calibration member may form an exterior surface configured to support the optical measurement device and scatter photons of light emitted by the optical measurement device. The calibration operation may be performed based on arrival times of the scattered photons detected by the optical measurement device.

Abstract: An illustrative optical measurement system includes a light source configured to emit light directed at a target. The system further includes a detector configured to detect arrival times for photons of the light after the light is scattered by the target. The system further includes a temperature sensor configured to output a temperature signal representative of a temperature of the light source. The system further includes an optical sensor configured to output a power signal representative of an optical power level of the light emitted by the light source. The system further includes a driver circuit configured to output, based on the temperature signal and the power signal, an input current for the light source.

Abstract: An illustrative optical measurement device includes a light source configured to emit light pulses directed at a target of a user. The optical measurement device further includes a detector configured to detect arrival times for photons of the light pulses after the photons are scattered by the target. The optical measurement device further includes a processing unit configured to determine, while the optical measurement device is being worn by the user, an instrument response function (IRF) associated with the optical measurement device. The processing unit is further configured to generate, based on the arrival times of the photons at the detector, histogram data associated with the target. The processing unit is further configured to determine, based on the IRF and the histogram data, a property of the target.

Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.

Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.

Abstract: A field effect transistor (FET) includes a substrate, a back barrier disposed on the substrate, a channel disposed on the back barrier, a front barrier disposed on the channel, a source, and a drain, such that at least one of the front barrier and the back barrier includes an anti-barrier-conduction (ABC) spacer which reduces parasitic conduction on a path from the source to the drain through at least one of the front barrier and the back barrier, reduces ON-state leakage from the channel to gate or substrate of the FET via resonant tunneling, and reduces OFF-state leakage by presenting tall barriers to electrons as well as electron-holes. This results in a highly linear, low gate leakage, low parasitic conduction, and low noise operation of FET.

Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: A delivery device for delivering a detergent independently of a change in a viscidity of a detergent and a method of controlling the same are provided. The delivery device includes a detergent storage; a pump configured to inject the detergent into a dissolving container a motor configured to drive the pump; a delivery container communicated with the detergent storage via a first one-way valve; the dissolving container communicated with the delivery container via a second one-way valve, the first and second one-way valves having opposite liquid conducting directions; a piston disposed in the delivery container; a crank-connecting rod mechanism constituted by the delivery container, the piston, a piston rod and a crankshaft; a contact switch; a cam disposed on a main journal of the crankshaft, a point of an outer contour of the cam triggering the contact switch to turn on and off once when the crankshaft makes one revolution.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.